SIHG16N50C-E3 Datasheet SIHG16N50C-E3 | P4-P6

www.vishay.com Document Number: 91418

4 S10-1355-Rev. A, 14-Jun-10

SiHG16N50C

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Fig. 9a - Switching Time Test Circuit

Fig. 9b - Switching Time Waveforms

V

DS

, Drain-to-Source Voltage (V)

C, Capacitance (pF)

1 10 100 1000

2400

2000

1600

1200

800

400

0

V

GS

= 0 V, f = 1MHz

C

iss

= C

gs

+C

gd

C

ds

SHORTED

C

rss

= C

gd

C

oss

= C

ds

+ C

gd

C

oss

C

iss

C

rss

2800

Q

G

, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

0 20406080

0

4

8

12

16

20

24

I

D

= 16 A

V

DS

= 400 V

V

DS

= 250 V

V

DS

= 100 V

0.1

1

10

100

V

SD

, Source-to-Drain Voltage (V)

I

SD

, Reverse Drain Current (A)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

V

GS

= 0 V

T

J

= 25 °C

T

J

= 150 °C

0.1

1

10

100

V

DS

, Drain-to-Source Voltage (V)

I

D

, Drain-to-Source Current (A)

10 100 1000

100 µs

T

C

= 25 °C

T

J

= 150 °C

Single Pulse

10 ms

1 ms

OPERATION IN THIS AREA

LIMITED BY R

DS(on)

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

Document Number: 91418 www.vishay.com

S10-1355-Rev. A, 14-Jun-10 5

SiHG16N50C

Vishay Siliconix

Fig. 10 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 11a - Unclamped Inductive Test Circuit

Fig. 11b - Unclamped Inductive Waveforms

Fig. 12a - Basic Gate Charge Waveform

Fig. 12b - Gate Charge Test Circuit

1

0.1

0.01

10

-4

10

-3

10

-2

0.1 1

t

1

, Rectangular Pulse Duration (s)

Thermal Response (Z

thJC

)

Single Pulse

(Thermal Response)

0.02

0.05

0.1

0.5

0.2

P

DM

t

1

t

2

Notes:

1. Duty Factor, D = t

1

/t

2

2. Peak T

j

= P

DM

x Z

thJC

+ T

C

A

R

G

I

AS

0.01

Ω

t

p

D.U.T.

L

V

DS

+

-

V

DD

Driver

A

15 V

20 V

t

p

V

DS

I

AS

Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

D.U.T.

V

DS

I

D

I

G

3 mA

V

GS

0.3 µF

50 kΩ

0.2 µF

12 V

Current regulator

Same type as D.U.T.

Current sampling resistors

+

-

www.vishay.com Document Number: 91418

6 S10-1355-Rev. A, 14-Jun-10

SiHG16N50C

Vishay Siliconix

Fig. 13 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91418

.

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied

voltage

Reverse

recovery

current

Body diode forward

current

V

GS

= 10 V

a

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

SIHG16N50C-E3

SIHG16N50C-E3

Products related to this Datasheet