MPC5125YVN400R

Freescale Semiconductor
Product Brief
Document Number: MPC5125PB
Rev. 2, 7/2009
Contents
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
This document contains
preview information on a new
product that may be in a design
phase or under development.
Freescale reserves the right to
change or discontinue this
product without notice.
Designed for telematics systems and high temperature
industrial applications, the MPC5125 32-bit embedded
controller is a device from Freescale Semiconductor's
mobileGT™ family containing the e300 Power
Architecture™
technology core. This core complies with
the Power Architecture embedded category, and
maintains binary compatible with other processors in the
mobileGT product family such as the MPC5121e and
MPC5200B. It offers a robust system performance with
a smaller package size, while bringing you the reliability
and familiarity of the proven Power Architecture
technology. An ecosystem of third-party vendors is
available to help simplify and speed system design. This
document provides an overview of the MPC5125
microcontroller features, including the major functional
components.
1 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.4 Chip Level Features. . . . . . . . . . . . . . . . . . . . . . . . . 3
2.5 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.5.1 e300 Processor Core . . . . . . . . . . . . . . . . . . 3
2.5.2 Display Interface Unit (DIU) . . . . . . . . . . . . . 4
2.5.3 USB Controller . . . . . . . . . . . . . . . . . . . . . . . 4
2.5.4 Direct Memory Access (DMA) Controller. . . 4
2.5.5 DDR SDRAM Memory Controller. . . . . . . . . 4
2.5.6 32 KB On-chip SRAM . . . . . . . . . . . . . . . . . 4
2.5.7 Fast Ethernet Controller (FEC) . . . . . . . . . . 4
2.5.8 NAND Flash Interface . . . . . . . . . . . . . . . . . 5
2.5.9 Local Plus Bus (LPC) Interface . . . . . . . . . . 5
2.5.10 Secure Digital Host Controller (SDHC) . . . . 5
2.5.11 Controller Area Network (CAN) . . . . . . . . . . 5
2.5.12 Integrated Circuit Communication (I
2
C) . . . . 5
2.5.13 Programmable Serial Controller (PSC) . . . . 5
2.5.14 J1850 Byte Data Link Controller (BDLC)
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5.15 General Purpose I/Os (GPIO) . . . . . . . . . . . 6
2.5.16 On-chip Real-time Clock (RTC) . . . . . . . . . . 6
2.5.17 IC Identification Module (IIM) . . . . . . . . . . . . 6
2.5.18 On-chip Temperature Sensor. . . . . . . . . . . . 6
2.5.19 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5.20 System Timer. . . . . . . . . . . . . . . . . . . . . . . . 7
2.5.21 IEEE 1149.1 Compliant JTAG Boundary Scan. 7
3 Developer Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MPC5125 Product Brief
MPC5125 Product Brief, Rev. 2
Applications
Freescale Semiconductor2
1 Applications
The MPC5125 is well suited to network-connected automotive and industrial applications that require
complex real-time control and robust performance, such as the following:
Telematics
Industrial automation
Avionics
Robotics
Motion control
Utilities / Power Management
Medical instrumentation
2Features
2.1 Block Diagram
Figure 1 shows a top-level block diagram of the MPC5125.
Figure 1. Simplified MPC5125 Block Diagram
Display SDR, Mobile DDR, DDR1/2 Memory
Functionally
Multiplexed I/O
FEC1
FEC2
USB1
ULPI
USB2
ULPI
200 MHz AHB (32 bits)
LPC
NFC
EMB
Multi-Port
Memory Controller
DIU
32 KB SRAM
DMA
64-Channel
e300
Power Architecture
32 KB instruction /
66 MHz IP BUS
TempSensor
Fuse
PMC
IPIC
WDT
GPT × 2
GPIO × 2
I
2
C×3
CAN × 4
J1850
SDHC × 2
PSC × 10
RTC
MPC5125
JTAG/COP
Clock/Reset
JTAG/COP
200 MHz CSB Bus (64 bits)
32 KB data cache
Features
MPC5125 Product Brief, Rev. 2
Freescale Semiconductor 3
2.2 Operating Parameters
As fast as 400 MHz
–40 to 125 °C junction temperature
2.3 Package
324-pin plastic ball grid array (TEPBGA)
2.4 Chip Level Features
Major features of the MPC5125 are as follows:
e300 Power Architecture processor core (enhanced version of the MPC603e core), operates as fast
as 400 MHz
Low power design
Display interface unit (DIU)
DDR1, DDR2, low-power mobile DDR (LPDDR), and 1.8 V/3.3 V SDR DRAM memory
controllers
32 KB on-chip SRAM
USB 2.0 OTG controller with ULPI interface
DMA subsystem
Flexible multi-function external memory bus (EMB) interface
NAND flash controller (NFC)
LocalPlus interface (LPC)
10/100Base Ethernet
•MMC/SD/SDIO card host controller (SDHC)
Programmable serial controller (PSC)
Inter-integrated circuit (I
2
C) communication interfaces
Controller area network (CAN)
J1850 byte data link controller (BDLC) interface
On-chip real-time clock (RTC)
On-chip temperature sensor
IC Identification module (IIM)
2.5 Module Features
The following is a brief summary of the functional blocks in the MPC5125. For more detailed information,
refer to the MPC5125 Reference Manual (MPC5125RM).
2.5.1 e300 Processor Core
Power Architecture instruction set

MPC5125YVN400R

Mfr. #:
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NXP / Freescale
Description:
Microprocessors - MPU POWERPC EMBEDDED SOC
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