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ISL6207CBZ

P1-P3P4-P6P7-P9P10-P10
4
FN9075.8
December 2, 2005
Absolute Maximum Ratings Thermal Information
Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (V
EN
, V
PWM
) . . . . . . . . . . . . . . . -0.3V to V
CC
+ 0.3V
BOOT Voltage (V
BOOT
). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V
BOOT to PHASE Voltage (V
BOOT-PHASE
) . . . . . . . . . . . -0.3V to 7V
PHASE Voltage . . . . . . . . . . . . . GND - 0.3V (DC) to V
BOOT
+ 0.3V
. . . . . . . . . GND - 5V (<100ns Pulse Width, 10µJ) to V
BOOT
+ 0.3V
UGATE Voltage . . . . . . . . . . V
PHASE
- 0.3V (DC) to V
BOOT
+ 0.3V
. . . . . . .V
PHASE
- 4V (<200ns Pulse Width, 20µJ) to V
BOOT
+ 0.3V
LGATE Voltage . . . . . . . . . . . . . . GND - 0.3V (DC) to V
VCC
+ 0.3V
. . . . . . . . . . . GND - 2V (<100ns Pulse Width, 4µJ) to V
VCC
+ 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 125°C
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-10°C to 100°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125°C
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
SOIC Package (Note 2) . . . . . . . . . . . . 110 N/A
QFN Package (Notes 3, 4). . . . . . . . . . 95 36
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current I
VCC
EN = LOW - - 5.0 A
Bias Supply Current I
VCC
PWM pin floating, V
VCC
= 5V - 30 - A
BOOTSTRAP DIODE
Forward Voltage V
F
V
VCC
= 5V, forward bias current = 2mA 0.45 0.60 0.65 V
PWM INPUT
Input Current I
PWM
V
PWM
= 5V - 250 - A
V
PWM
= 0V - -250 - A
PWM Three-State Rising Threshold V
VCC
= 5V - - 1.7 V
PWM Three-State Falling Threshold V
VCC
= 5V 3.3 - - V
Three-State Shutdown Holdoff Time V
VCC
= 5V, temperature = 25°C - 300 - ns
EN INPUT
EN LOW Threshold 1.0 - - V
EN HIGH Threshold --2.0V
SWITCHING TIME
UGATE Rise Time (Note 5) t
RUGATE
V
VCC
= 5V, 3nF Load - 8 - ns
LGATE Rise Time (Note 5) t
RLGATE
V
VCC
= 5V, 3nF Load - 8 - ns
UGATE Fall Time (Note 5) t
FUGATE
V
VCC
= 5V, 3nF Load - 8 - ns
LGATE Fall Time (Note 5) t
FLGATE
V
VCC
= 5V, 3nF Load - 4 - ns
UGATE Turn-Off Propagation Delay t
PDLUGATE
V
VCC
= 5V, Outputs Unloaded - 18 - ns
LGATE Turn-Off Propagation Delay t
PDLLGATE
V
VCC
= 5V, Outputs Unloaded - 15 - ns
ISL6207
5
FN9075.8
December 2, 2005
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500k resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
EN (Pin 7 for SOIC-8, Pin 6 for QFN)
EN is the enable input pin. Connect this pin to HIGH to
enable, and LOW to disable, the IC. When disabled, the IC
draws less than 1A bias current.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
Operation
Designed for speed, the ISL6207 dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLLGATE
], the lower gate begins to fall. Typical fall
times [t
FLGATE
] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the LGATE
voltage and determines the upper gate delay time
[t
PDHUGATE
], based on how quickly the LGATE voltage drops
below 1V. This prevents both the lower and upper MOSFETs
from conducting simultaneously, or shoot-through. Once this
delay period is completed, the upper gate drive begins to rise
[t
RUGATE
], and the upper MOSFET turns on.
UGATE Turn-On Propagation Delay t
PDHUGATE
V
VCC
= 5V, Outputs Unloaded 10 20 30 ns
LGATE Turn-On Propagation Delay t
PDHLGATE
V
VCC
= 5V, Outputs Unloaded 10 20 30 ns
OUTPUT
Upper Drive Source Resistance R
UGATE
500mA Source Current - 1.0 2.5
-10°C to 85°C - 1.0 2.2
Upper Driver Source Current (Note 5) I
UGATE
V
UGATE-PHASE
= 2.5V - 2.0 - A
Upper Drive Sink Resistance R
UGATE
500mA Sink Current - 1.0 2.5
-10°C to 85°C - 1.0 2.2
Upper Driver Sink Current (Note 5) I
UGATE
V
UGATE-PHASE
= 2.5V - 2.0 - A
Lower Drive Source Resistance R
LGATE
500mA Source Current - 1.0 2.5
-10°C to 85°C - 1.0 2.2
Lower Driver Source Current (Note 5) I
LGATE
V
LGATE
= 2.5V - 2.0 - A
Lower Drive Sink Resistance R
LGATE
500mA Sink Current - 0.4 1.0
-10°C to 85°C - 0.4 0.8
Lower Driver Sink Current (Note 5) I
LGATE
V
LGATE
= 2.5V - 4.0 - A
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL6207
6
FN9075.8
December 2, 2005
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
PDLUGATE
] is encountered before the
upper gate begins to fall [t
FUGATE
]. Again, the adaptive shoot-
through circuitry determines the lower gate delay time
t
PDHLGATE
. The upper MOSFET gate-to-source voltage is
monitored, and the lower gate is allowed to rise, after the
upper MOSFET gate-to-source voltage drops below 1V. The
lower gate then rises [t
RLGATE
], turning on the lower
MOSFET.
This driver is optimized for converters with large step down
ratio, such as those used in a mobile-computer core voltage
regulator. The lower MOSFET is usually sized much larger.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4 on-resistance
and 4A sink current capability enable the lower gate driver to
absorb the current injected to the lower gate through the
drain-to-gate capacitor of the lower MOSFET and prevent a
shoot through caused by the high dv/dt of the phase node.
Three-State PWM Input
A unique feature of the ISL6207 and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the output drivers are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
During start-up, PWM should be in the three-state position
(1/2 V
CC
). However, with rising V
CC
, the active tracking
elements for PWM are not active until V
CC
> 1.2V, which
leaves PWM in a high impedance (undetermined) state;
therefore, a 500k resistor must be place from the PWM pin
to GND.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
bootstrap capacitor can be chosen from the following
equation:
where Q
GATE
is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The V
BOOT
term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
GATE
, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125F is required.
PWM
UGATE
LGATE
t
PDLLGATE
t
FLGATE
t
PDHUGATE
t
RUGATE
t
PDLUGATE
t
FUGATE
t
PDHLGATE
t
RLGATE
1V
1V
FIGURE 1. TIMING DIAGRAM
C
BOOT
Q
GATE
V
BOOT
------------------------
ISL6207
P1-P3P4-P6P7-P9P10-P10

ISL6207CBZ

Mfr. #:
Buy ISL6207CBZ
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers VERSION OF ISL6207CB
Lifecycle:
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