www.nxp.com
NXP, the NXP logo and the SafeAssure logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners. Arm, Cortex and
TrustZone are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. NEON is a trademark of Arm Limited (or its subsidiaries) in the EU and/or
elsewhere. © 2017 NXP B.V.
Document Number: S32V234FS REV 3
SafeAssure PROGRAM
Functional safety. Simplified.
Our SafeAssure functional safety program is designed to help system manufacturers more
easily achieve system compliance with International Standards Organization (ISO) 26262 and
International Electrotechnical Commission (IEC) 61508 functional safety standards. The program
highlights our solutions—hardware and software—that are optimally designed to support
functional safety implementations and come with a rich set of enablement collateral.
For more information, visit www.nxp.com/SafeAssure.
S32V234 BLOCK DIAGRAM
Key Features Benefits
Designed and manufactured to satisfy automotive reliability
and ISO 26262 ASIL B/C functional safety requirements
Enables adherence to ISO 26262 ASIL B standard for automotive safety applications
Quad 1 GHz Arm
®
Cortex
®
-A53 core + Arm NEON
™
core platform
9.2 K DMIPS processing horsepower (without acceleration) for management of ADAS tasks
Arm Cortex-M4 core at 133 MHz for I/O control and
AUTOSAR OS
Enables automotive OS such as AUTOSAR to control interfaces to external devices without impacting
Cortex-A53 performance
Embedded security Security engine together with Arm TrustZone
®
technology provides protection against IP theft and
malicious hacking
Dual APEX-2 image processing engine Allows high-performance, low-power processing of incoming image data
Image signal processor Performs image housekeeping tasks such as HDR and color conversion, plus some dedicated image
processing tasks
3-D graphics processing unit (GPU) For rendering 3-D images; may also be used for additional image analysis tasks
Video input: dual MIPI-SCI; dual video input unit (VIU) Supports mono, stereo and surround view camera inputs; H.264 decode and encode also supported
Memory interfaces DRAM support for LPDDR2/DDR3L/DDR3 for high-bandwidth data access, plus dual QuadSPI
for external flash
The S32V234 is part of our SafeAssure
®
program and designed specifically to address ISO 26262 ASIL B/C functional safety requirements.
S32V234 MCU FAMILY
External Memory
Ext. Memory I/F
LP-DDR2/DDR3
DDR Ctrl + ECC
DDR Quad SPI
Internal Memory
4 MB RAM with ECC
System Control
and Support
FCCU and M/L BIST
T-Sensor
CRC Computing
Safe DMA
DEBUG and Trace Unit
Security
CSE + Flashless
Fabric
ARM AMBA
®
AXI3/ACE Interconnect 128-bit with MPU
Dual Camera Interfaces
2 x MIPI CSI2
Image Signal Processing
HDR
Color Conversion
Tone Mapping
2 x Parallel 16-bit
Image Cognition Proc.
Image Cognition Proc.
L-mem
Sequencer
32 CU
32 CU
DMA
APEX2CL
Image Processing Platform
Gfx & Display
3D GPU
DCU 18/24 bits RGB
Video Codec H.264
8-12 bits Encoder
8-12 bit Decoder
JPEG/H.264
Vision Platform
CPU Platform
ARM Cortex-A53 ARM Cortex-A53
ARM
®
Cortex
®
-A53
32 KB I-cache
I-Cache
2 way
ARM NEON
TM
D-Cache
4 way
NEON
L2 Cache–512 KB + ECC
SCU
Cortex-M4
Connectivity
2 x CAN-FD 64 Msg
Dual Ch. FlexRay™ 128 MSG.
Gigabit Ethernet Control
5 Gbit/s PCle
®
1 lane 2 x LinFlex Ctrl & 3 x I
2
C 4 x dSPI (4 cs)
2 x eTimers 2 x SAR ADC 12 bits 1 Ms/s 1 x SD-HC
Zipwire
®
32 KB D-cache 32 KB I-cache
I-Cache
2 way
D-Cache
4 way
32 KB D-cache
ARM Cortex-A53
L-mem
Optional
S32V234 BLOCK DIAGRAM
External Memory
Ext. Memory I/F
LP-DDR2/DDR3
DDR Ctrl + ECC
DDR Quad SPI
Internal Memory
4 MB RAM with ECC
System Control
and Support
FCCU and M/L BIST
T-Sensor
CRC Computing
Safe DMA
DEBUG and Trace Unit
Security
CSE + Flashless
Fabric
ARM AMBA
®
AXI3/ACE Interconnect 128-bit with MPU
Dual Camera Interfaces
2 x MIPI CSI2
Image Signal Processing
HDR
Color Conversion
Tone Mapping
2 x Parallel 16-bit
Image Cognition Proc.
Image Cognition Proc.
L-mem
Sequencer
32 CU
32 CU
DMA
APEX2CL
Image Processing Platform
Gfx & Display
3D GPU
DCU 18/24 bits RGB
Video Codec H.264
8-12 bits Encoder
8-12 bit Decoder
JPEG/H.264
Vision Platform
CPU Platform
ARM Cortex-A53 ARM Cortex-A53
ARM
®
Cortex
®
-A53
32 KB I-cache
I-Cache
2 way
ARM NEON
TM
D-Cache
4 way
NEON
L2 Cache–512 KB + ECC
SCU
Cortex-M4
Connectivity
2 x CAN-FD 64 Msg
Dual Ch. FlexRay™ 128 MSG.
Gigabit Ethernet Control
5 Gbit/s PCle
®
1 lane 2 x LinFlex Ctrl & 3 x I
2
C 4 x dSPI (4 cs)
2 x eTimers 2 x SAR ADC 12 bits 1 Ms/s 1 x SD-HC
Zipwire
®
32 KB D-cache 32 KB I-cache
I-Cache
2 way
D-Cache
4 way
32 KB D-cache
ARM Cortex-A53
L-mem
Optional
