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72285L15PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit
setup procedure. D = 32,768 for IDT72275 and 65,536 for IDT72285.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
t
REF
t
ENH
4674 drw 14
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
W
1
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
t
ENS
t
ENH
(3)
t
A
t
A
(3)
(5)
t
RTS
t
RTS
t
PAF
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
20
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit
setup procedure. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
SEN
SI
4674 drw 16
tENH
t
ENS
t
LDS
LD
t
DS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
t
ENH
BIT X
(1)
t
LDH
t
LDH
t
LDH
t
DH
t
REF
t
ENH
4674 drw 15
t
ENS
W
x
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0 - Qn
t
SKEW2
12
1
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
W
1
t
ENH
(4)
(5)
3
4
t
ENH
W
3
t
RTS
t
RTS
t
PAF
t
A
t
A
NOTE:
1. X = 14 for the IDT72275 and X = 15 for the IDT72285.
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
In FWFT mode: D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
(3)
REN
4674 drw 19
t
ENS
t
ENH
t
ENS
D - (m+1) words in FIFO
(2)
t
SKEW2
1
2
12
D-(m+1) words
in FIFO
(2)
t
PAF
t
PAF
D - m words in FIFO
(2)
RCLK
LD
REN
Q
0 - Q15
t
LDH
t
LDS
t
ENS
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
t
ENH
4674 drw18
t
CLK
t
A
t
A
t
LDH
t
ENH
t
CLKH
t
CLKL
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
LD
WEN
D
0 - D15
4674 drw 17
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

72285L15PF8

Mfr. #:
Buy 72285L15PF8
Manufacturer:
IDT
Description:
FIFO IDT
Lifecycle:
New from this manufacturer.
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