21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
In FWFT mode: D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAF
RCLK
(3)
REN
4674 drw 19
t
ENS
t
ENH
t
ENS
D - (m+1) words in FIFO
(2)
t
SKEW2
1
2
12
D-(m+1) words
in FIFO
(2)
t
PAF
t
PAF
D - m words in FIFO
(2)
RCLK
LD
REN
Q
0 - Q15
t
LDH
t
LDS
t
ENS
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
t
ENH
4674 drw18
t
CLK
t
A
t
A
t
LDH
t
ENH
t
CLKH
t
CLKL
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
LD
WEN
D
0 - D15
4674 drw 17
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)