MAX1420ECM+D Datasheet MAX1420CCM+D, MAX1420CCM+TD, MAX1420ECM+TD | P10-P12

MAX1420

12-Bit, 60Msps, 3.3V, Low-Power ADC

with Internal Reference

10 ______________________________________________________________________________________

Detailed Description

The MAX1420 uses a 12-stage, fully-differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Each sample moves through a pipeline stage

every half-clock cycle, including the delay through the

output latch. The latency is seven clock cycles.

A 2-bit (2-comparator) flash ADC converts the held-

input voltage into a digital code. The following digital-

to-analog converter (DAC) converts the digitized result

back into an analog voltage, which is then subtracted

from the original held-input signal. The resulting error

signal is then multiplied by two, and the product is

passed along to the next pipeline stage. This process is

repeated until the signal has been processed by all 12

stages. Each stage provides a 1-bit resolution. Digital

error correction compensates for ADC comparator off-

sets in each pipeline stage and ensures no missing

codes.

Input Track-and-Hold Circuit

Figure 2 displays a simplified functional diagram of the

input track-and-hold (T/H) circuit in both track-and-hold

mode. In track mode, switches S1, S2a, S2b, S4a, S4b,

S5a, and S5b are closed. The fully-differential circuit

passes the input signal to the two capacitors C2a and

C2b through switches S4a and S4b. Switches S2a and

S2b set the common mode for the operational transcon-

ductance amplifier (OTA) input, and open simultane-

ously with S1, sampling the input waveform. The result-

ing differential voltage is held on capacitors C2a and

C2b. Switches S4a and S4b are then opened before

S3a, S3b, S4C are closed. The OTA is used to charge

capacitors C1a and C1b to the same values originally

held on C2a and C2b. This value is then presented to

the first stage quantizer and isolates the pipeline from

the fast-changing input. The wide input bandwidth T/H

amplifier allows the MAX1420 to track and sample/hold

analog inputs of high frequencies beyond Nyquist. The

analog inputs INP to INN can be driven either differen-

tially or single-ended. Match the impedance of INP and

INN and set the common-mode voltage to midsupply

(AV

/2) for optimum performance.

Analog Input and Reference Configuration

The full-scale range of the MAX1420 is determined by

the internally generated voltage difference between

REFP (AV

/2 + V

REFIN

/4) and REFN (AV

/2 -

REFIN

/4). The MAX1420’s full-scale range is adjustable

through REFIN, which provides high input impedance

for this purpose. REFP, CML (AV

/2), and REFN are

internally buffered low impedance outputs.

An internal 2.048V precision bandgap reference sets

the full-scale range of the ADC. A flexible reference

structure accommodates an internal reference, or exter-

nally applied buffered or unbuffered reference for appli-

T/H

OUT

FLASH

ADC

DAC

2 BITS

MDAC

STAGE 1 STAGE 2

D11–D0

DIGITAL CORRECTION LOGIC

STAGE 12

TO NEXT

STAGE

MAX1420

Figure 1. Pipelined Architecture—Stage Blocks

S3b

S3a

CML

S5bS2b

S5a

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

OTA

INTERNAL

BIAS

CML

S2a

MAX1420

Figure 2. Internal Track-and-Hold Circuit

MAX1420

12-Bit, 60Msps, 3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 11

cations that require increased accuracy and a different

input voltage range.

The MAX1420 provides three modes of reference oper-

ation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, the on-chip 2.048V

bandgap reference is active and REFIN, REFP, CML,

and REFN are left floating. For stability purposes,

bypass REFIN, REFP, REFN and CML with a capacitor

network of 0.22µF in parallel with a 1nF capacitor to

AGND.

In buffered external reference mode, the reference volt-

age levels can be adjusted externally by applying a

stable and accurate voltage at REFIN.

In unbuffered external reference mode, REFIN is con-

nected to AGND, thereby deactivating the on-chip

buffers of REFP, CML, and REFN. With their buffers

shut down, these nodes become high impedance and

can be driven by external reference sources, as shown

in Figure 3.

Clock Inputs (CLK,

CLK

)

The MAX1420’s CLK and CLK inputs accept both dif-

ferential and single-ended input operation and accept

CMOS-compatible clock signals. If CLK is driven with a

single-ended clock signal, bypass CLK with a 0.1µF

capacitor to AGND. Since the interstage conversion of

the device depends on the repeatability of the rising

and falling edges of the external clock, use a clock with

low jitter and fast rise and fall times (< 2ns). Sampling

occurs on the rising edge of the clock signal, requiring

this edge to have the lowest possible jitter. Any signifi-

cant aperture jitter would limit the SNR performance of

the ADC according to the following relationship:

where f

represents the analog input frequency and

is the aperture jitter. Clock jitter is especially critical

for high input frequency applications. The clock input

should always be considered as an analog signal and

routed away from any analog or digital signal lines.

The MAX1420 clock input operates with a voltage

threshold set to AV

/2. Clock inputs must meet the

specifications for high and low periods as stated in the

Electrical Characteristics.

SNR

IN AJ

=×

××

log

MAX1420

REFIN

REFN

50Ω

0.5V

50Ω

CML

1nF

0.22μF

1nF0.22μF

AGND

MAX4284

REFP

Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled

12 ______________________________________________________________________________________

MAX1420

12-Bit, 60Msps, 3.3V, Low-Power ADC

with Internal Reference

Figure 4 shows a simplified model of the clock input cir-

cuit. This circuit consists of two 10kΩ resistors to bias

the common-mode level of each input. This circuit may

be used to AC-couple the system clock signal to the

MAX1420 clock input.

Output Enable (

), Power-Down (PD)

and Output Data (D0–D11)

In addition to low operating power, the MAX1420 fea-

tures two power-down modes: reference power-down

and shutdown mode. In reference power-down, the in-

ternal bandgap reference is deactivated, which results in

a typical 2mA supply current reduction. A full shutdown

mode is available to maximize power savings during idle

periods.

The MAX1420 provides parallel, offset binary, CMOS-

compatible three-state outputs.

With OE high, the digital outputs enter a high-imped-

ance state. If OE is held low with PD high, the outputs

are latched at the last digital output code prior to the

power-down. All data outputs, D0 (LSB) through D11

(MSB), are TTL/CMOS logic-compatible. There is a

seven clock-cycle latency between any particular sam-

ple and its valid output data. The output coding is in off-

set binary format (Table 1).

The capacitive load on the digital outputs D0 through

D11 should be kept as low as possible (≤10pF), to

avoid large digital currents that could feed back into

the analog portion of the MAX1420, thereby degrading

its performance. The use of buffers (e.g., 74LVCH16244)

on the digital outputs of the ADC can further isolate the

digital outputs from heavy capacitive loads. To further

improve the dynamic performance of the MAX1420,

add small-series resistors of 100Ω to the digital output

paths, close to the ADC.

Figure 5 displays the timing relationship between out-

put enable and data output.

System Timing Requirements

Figure 6 depicts the relationship between the clock

input, analog input, and valid data output. The

MAX1420 samples the analog input signal on the rising

edge of CLK (falling edge of CLK) and output data is

valid seven clock cycles (latency) later.

Applications Information

Figure 7 depicts a typical application circuit containing

a single-ended to differential converter. The internal ref-

erence provides an AV

/2 output voltage for level

shifting purposes. The input is buffered and then split to

a voltage follower and inverter. A lowpass filter at the

input suppresses some of the wideband noise associated

D11–D0

10kΩ

VDD

ADC

CLK

INN

INP

AGND

MAX1420

Figure 4. Simplified Clock Input Circuit

OUTPUT

DATA D11–D0

HIGH-ZHIGH-Z

VALID DATA

Figure 5. Output Enable Timing

Table 1. MAX1420 Output Code for

Differential Inputs

DIFFERENTIAL

INPUT VOLTAGE*

DIFFERENTIAL

INPUT

OFFSET

BINARY

REF

× 2047/2048

+FULL SCALE -

1LSB

1111 1111 1111

REF

× 2046/2048

+FULL SCALE -

2LSB

1111 1111 1110

REF

× 1/2048 + 1 LSB

1000 0000 0001

0 Bipolar Zero

1000 0000 0000

-V

REF

× 1/2048 - 1 LSB

0111 1111 1111

-V

REF

× 2046/2048

-FULL SCALE +

1 LSB

0000 0000 0001

-V

REF

× 2047/2048

-FULL SCALE

0000 0000 0000

* V

REF

= V

REFP

- V

REFN

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

MAX1420ECM+D

Mfr. #:

Buy MAX1420ECM+D

Manufacturer:

Maxim Integrated

Description:

IC ADC 12BIT 60MSPS 48LQFP

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MAX1420ECM+D

MAX1420ECM+D

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