MAX1420
12-Bit, 60Msps, 3.3V, Low-Power ADC
with Internal Reference
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Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External 2.048V reference applied to REFIN.
Note 3: Internal reference disabled. V
REFIN
= 0, V
REFP
= 2.162V, V
CML
= 1.65V, and V
REFN
= 1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1420.
Note 6: V
DIFF
= V
REFP
- V
REFN
.
Note 7: Input bandwidth is measured at a -3dB level.
Note 8: V
REFIN
is internally biased to 2.048V through a 10kΩ resistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in V
AVDD
, using the internal reference.
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, V
IN
= ±1.024V, differential input voltage at -0.5dBFS, internal reference, f
CLK
=
62.5MHz (50% duty cycle); digital output load C
L
= 10pF, ≥+25°C guaranteed by production test, <+25°C guaranteed by design and
characterization. Typical values are at T
A
= +25°C.)
Typical Operating Characteristics
(V
AVDD
= V
DVDD
= 3.3V, AGND = DGND = 0, V
IN
= ±1.024V, differential input drive, A
IN
= -0.5dBFS, f
CLK
= 60.006MHz (50% duty
cycle), digital output load C
L
= 10pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
