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8432DY-101LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
IDT
™
/ ICS
™
700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER 10 ICS8432DY-101 REV. C APRIL 10, 2007
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4A to 4E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
IDT
™
/ ICS
™
700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER 11 ICS8432DY-101 REV. C APRIL 10, 2007
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
V
CC
- 2V
50Ω 50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT
FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω 125Ω
84Ω 84Ω
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 5B. LVPECL OUTPUT TERMINATIONFIGURE 5A. LVPECL OUTPUT TERMINATION
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
IDT
™
/ ICS
™
700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER 12 ICS8432DY-101 REV. C APRIL 10, 2007
ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS8432-101 layout example used in this
layout guideline is shown in Figure 6A. The ICS8432-101
recommended PCB board layout for this example is shown in
Figure 6B. This layout example is used as a general guideline.
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
C16
10u
Termination A
U1
8432-101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TEST
VDD
FOUT1/2
nFOUT1/2
VCCO
FOUT
nFOUT
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VDDA
nCLK_SEL
REF_IN
CLK
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
nCLK
R1
125
VCCA
TL2
Zo = 50 Ohm
TEST
IN-
IN-
VCC
S_CLOCK
VCC
R3
125
C11
0.01u
XTAL_SEL
R3
50
S_LOAD
R7
10
TL1
Zo = 50 Ohm
MR
IN+
R4
84
FOUT
R2
84
S_DATA
R1
50
C15
0.1u
nCLK
CLK
VCC
IN+
Termination B
(not shown in
the layout)
FOUTN
R2
50
C14
0.1u
VCC
The layout in the actual system will depend on the selected
component types, the density of the components, the density
of the traces, and the stack up of the P.C. board.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

8432DY-101LF

Mfr. #:
Buy 8432DY-101LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 2 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
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