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74AHCT259PW,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 15 May 2008 10 of 17
NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
Measurement points are given in Table 9.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Address input to output propagation delays
001aah122
An input
Qn output
t
PHL
t
PLH
GND
V
CC
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 9.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Enable input to output propagation delays and pulse width
001aah121
LE input
Qn output
t
PHL
t
PLH
t
W
V
M
V
OH
V
CC
GND
V
CC
GND
V
OL
V
M
D input
Measurement points are given in Table 9.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Conditional reset input to output propagation delays
001aah124
MR input
Qn output
t
PHL
t
W
V
M
V
OH
V
CC
GND
V
OL
V
M
74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 15 May 2008 11 of 17
NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 9. Data input to latch enable input set-up and hold times
001aah125
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
CC
V
OH
V
OL
V
CC
Qn output Q = D Q = D
LE input
D input
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 10. Address input to latch enable input set-up and hold times
001aah126
V
M
ADDRESS STABLE
V
M
t
h
t
su
V
CC
GND
V
CC
GND
LE input
An input
Table 9. Measurement points
Type Input Output
V
M
V
M
74AHC259 0.5 × V
CC
0.5 × V
CC
74AHCT259 1.5 V 0.5 × V
CC
74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 15 May 2008 12 of 17
NXP Semiconductors
74AHC259; 74AHCT259
8-bit addressable latch
Test data is given in Table 10.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 11. Load circuitry for measuring switching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
Table 10. Test data
Type Input Load Test
V
I
t
r
, t
f
C
L
74AHC259 V
CC
≤ 3.0 ns 15 pF, 50 pF t
PLH
, t
PHL
74AHCT259 3.0 V ≤ 3.0 ns 15 pF, 50 pF t
PLH
, t
PHL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

74AHCT259PW,112

Mfr. #:
Buy 74AHCT259PW,112
Manufacturer:
NXP Semiconductors
Description:
IC 8BIT ADDRESSBL LATCH 16-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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