NCP565, NCV565
www.onsemi.com
7
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
30
20
10
0
Start 1.0 kHz Stop 100 kHz
NOISE DENSITY (nV
rms
/ǰHz)
FREQUENCY (kHz)
Figure 17. Noise Density vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
Start 1.0 kHz Stop 100 kHz
FREQUENCY (kHz)
Figure 18. Noise Density vs. Frequency
V
in
= 3.0 V
V
out
= 0.9 V
I
out
= 10 mA
V
in
= 3.0 V
V
out
= 0.9 V
I
out
= 1.5 A
NOISE DENSITY (nV
rms
/ǰHz)
NOTE: Typical characteristics were measured with the same conditions as electrical characteristics.
APPLICATION INFORMATION
The NCP565 low dropout linear regulator provides
adjustable voltages at currents up to 1.5 A. It features ultra
fast transient response and low dropout voltage. These
devices contain output current limiting, short circuit
protection and thermal shutdown protection.
Input, Output Capacitor and Stability
An input bypass capacitor is recommended to improve
transient response or if the regulator is located more than a
few inches from the power source. This will reduce the
circuit’s sensitivity to the input line impedance at high
frequencies and significantly enhance the output transient
response. Different types and different sizes of input
capacitors can be chosen dependent on the quality of power
supply. A 150 mF OSCON 16SA150M type from Sanyo
should be adequate for most applications. The bypass
capacitor should be mounted with shortest possible lead or
track length directly across the regulators input terminals.
The output capacitor is required for stability. The NCP565
remains stable with ceramic, tantalum, and aluminum−
electrolytic capacitors with a minimum value of 1.0 mF with
ESR between 50 mW and 2.5 W. The NCP565 is optimized
for use with a 150 mF OSCON 16SA150M type in parallel
with a 10 mF OSCON 10SL10M type from Sanyo. The
10 mF capacitor is used for best AC stability while 150 mF
capacitor is used for achieving excellent output transient
response. The output capacitors should be placed as close as
possible to the output pin of the device. If not, the excellent
load transient response of NCP565 will be degraded.
Adjustable Operation
The typical application circuit for the adjustable output
regulators is shown in Figure 2. The adjustable device
develops and maintains the nominal 0.9 V reference voltage
between Adj and ground pins. A resistor divider network R1
and R2 causes a fixed current to flow to ground. This current
creates a voltage across R1 that adds to the 0.9 V across R2
and sets the overall output voltage.
The output voltage is set according to the formula:
V
out
+ V
ref
ǒ
R1 ) R2
R2
Ǔ
* I
Adj
R2
The adjust pin current, I
Adj
, is typically 30 nA and
normally much lower than the current flowing through R1
and R2, thus it generates a small output voltage error that can
usually be ignored.
Load Transient Measurement
Large load current changes are always presented in
microprocessor applications. Therefore good load transient
performance is required for the power stage. NCP565 has
the feature of ultra fast transient response. Its load transient
responses in Figures 13 through 16 are tested on evaluation
board shown in Figure 19. On the evaluation board, it
consists of NCP565 regulator circuit with decoupling and
filter capacitors and the pulse controlled current sink to
obtain load current transitions. The load current transitions
are measured by current probe. Because the signal from
current probe has some time delay, it causes
un−synchronization between the load current transition and
output voltage response, which is shown in Figures 13
through 16.
NCP565, NCV565
www.onsemi.com
8
NCP565
Evaluation Board
GEN
GND
V
RL
GND
Scope Voltage Probe
+
+
Pulse
Figure 19. Schematic for Transient Response Measurement
V
out
−V
CC
V
in
PCB Layout Considerations
Good PCB layout plays an important role in achieving
good load transient performance. Because it is very sensitive
to its PCB layout, particular care has to be taken when
tackling Printed Circuit Board (PCB) layout. The figures
below give an example of a layout where parasitic elements
are minimized. For microprocessor applications it is
customary to use an output capacitor network consisting of
several capacitors in parallel. This reduces the overall ESR
and reduces the instantaneous output voltage drop under
transient load conditions. The output capacitor network
should be as close as possible to the load for the best results.
The schematic of NCP565 typical application circuit, which
this PCB layout is base on, is shown in Figure 20. The output
voltage is set to 3.3 V for this demonstration board according
to the feedback resistors in the Table 1.
Figure 20. Schematic of NCP565 Typical Application Circuit
V
in
V
out
NCP565
GND
Adj
C
1
150 m
R
2
15.8 k
V
out
V
in
GND
C
2
150 m
NC
C
4
10 m
C
3
150 m
GND
C
3
150 m
C
6
5.6 p
R
1
42.2 k
2
1
3
5
4
NCP565, NCV565
www.onsemi.com
9
Figure 21. Top Layer
Figure 22. Bottom Layer
Figure 23. Silkscreen Layer
D1
C1
C2
C3
C4
C5
C6
GND
R1
R2
GND
VIN VOUT
NCP565
ON Semiconductor
www.onsemi.com
July, 2003

NCP565V12EVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Management IC Development Tools ANA 1.2V EVAL BD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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