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840001BGI-25LF

P1-P3P4-P6P7-P9P10-P12P13-P13
840001I-25 Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 15, 20167
APPLICATION INFORMATION
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT PINS
840001I-25 Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 15, 20168
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 840001I-25.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 840001I-25 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Core and Output Power Dissipation
• Power (core, output) = V
DD_MAX
* (I
DD
+ I
DDO
) = 3.465V * (83mA + 2mA) = 294.5mW
LVCMOS Output Power Dissipation
• Output Impedance R
OUT
Power Dissipation due to Loading 50Ω to V
DDO
/2
Output Current I
OUT
= V
DDO_MAX
/ [2 * (50Ω + R
OUT
)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.6mA
• Power Dissipation on the R
OUT
per LVCMOS output
Power (R
OUT
) = R
OUT
* (I
OUT
)
2
= 15Ω * (26.6mA)
2
= 10.6mW per output
• Dynamic Power Dissipation at 156.25MHz
Power (156.25MHz) = C
PD
* Frequency * (V
DDO
)
2
= 6pF * 156.25MHz * (3.465V)
2
= 11.26mW per output
Total Power Dissipation
• Total Power
= Power (core, output) + Power Dissipation (R
OUT
) + Dyamic Power Dissipation (156.25MHz)
= 294.5mW + 10.6mW + 11.26mW
= 316.4mW
840001I-25 Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 15, 20169
TABLE 5. THERMAL RESISTANCE θ
JA
FOR 8-LEAD TSSOP, FORCED CONVECTION
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air fl ow of 1meter per second and a multi-layer board, the appropriate value is 125.5°C/W per Table 5.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.316W * 125.5°C/W = 124.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the
type of board (multi-layer).
θ
JA
by Velocity (Meters Per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W
P1-P3P4-P6P7-P9P10-P12P13-P13

840001BGI-25LF

Mfr. #:
Buy 840001BGI-25LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 1 LVCMOS OUT CLOCK GEN
Lifecycle:
New from this manufacturer.
Delivery:
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