840001I-25 Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 15, 20163
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
129.5°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 83 mA
I
DDO
Output Supply Current No Load 2 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 2.375 2.5 2.625 V
V
DDO
Output Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 80 mA
I
DDO
Output Supply Current No Load 2 mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
=2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
V
DD
= 3.465V 2 V
DD
+ 0.3 V
V
DD
= 2.625V 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage
V
DD
= 3.465V -0.3 0.8 V
V
DD
= 2.625V -0.3 0.7 V
I
IH
Input High Current
REF_IN,
SEL_[0:2]
V
DD
= V
IN
= 3.465V or 2.625V 5 µA
I
IL
Input Low Current
REF_IN,
SEL_[0:2]
V
DD
= 3.465V or 2.625V, V
IN
= 0V -150 µA
V
OH
Output High Voltage; NOTE 1
V
DDO
= 3.465V 2.6 V
V
DDO
= 2.625V 1.8 V
V
OL
Output Low Voltage; NOTE 1 V
DDO
= 3.465V or 2.625V 0.6 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information Section,
“Output Load Test Circuit” diagrams.