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AD7846JP

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AD7846
Rev. G | Page 12 of 24
S1
V
REF+
V
REF–
DAC1
SEGMENT 1
SEGMENT 16
S3
S15
S17
S16
S14
S4
S2
DAC2
DAC3
12-BIT DAC
DB11 TO DB0
DB15 TO DB12 DB15 TO DB12
R
R
V
OUT
R
IN
A3
A2
A1
08490-021
Figure 21. Digital-to-Analog Conversion
OUTPUT STAGE
The output stage of the AD7846 is shown in Figure 22. It is capable
of driving a 2 kΩ/1000 pF load. It also has a resistor feedback
network that allows the user to configure it for gains of 1 or 2.
Table 6 shows the different output ranges that are possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 µs
after the leading edge of
LDAC
. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. Thus, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC
is tied permanently low, the deglitching is not in
operation. and show the outputs of the
AD7846 without and with the deglitcher.
Figure 13 Figure 14
C1
LDAC
V
OUT
R
IN
DAC3
ONE
SHOT
10kΩ
10kΩ
08490-022
Figure 22. Output Stage
AD7846
Rev. G | Page 13 of 24
UNIPOLAR BINARY OPERATION
Figure 23 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586 +5 V reference.
Because R
IN
is tied to 0 V, the output amplifier has a gain of 2
and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, R
IN
should be tied to V
OUT
, configuring the output
stage for a gain of 1. Tabl e 8 gives the code table for the circuit
of Figure 23.
R
IN
V
OUT
DGND
+15
+5
V
V
CC
V
DD
V
REF+
V
REF–
R1
10kΩ
C1
1µF
SIGNAL
GROUND
–15V
*ADDITIONAL PINS
OMITTED FOR CLARITY
AD7846*
AD586
V
OUT
(0V TO +10V)
V
SS
2
5
4
67
21
5
20
6
4
8
8
08490-023
Figure 23. Unipolar Binary Operation
Table 8. Code Table for Figure 23
Binary Number in DAC Latch
MSB LSB
1
Analog Output (V
OUT
)
1111 1111 1111 1111 +10 (65,535/65,536) V
1000 0000 0000 0000 +10 (32,768/65,536) V
0000 0000 0000 0001 +10 (1/65,536) V
0000 0000 0000 0000 0 V
1
LSB = 10 V/2
16
= 10 V/65,536 = 152 µV.
Offset and gain can be adjusted in Figure 23 as follows:
• To adjust offset, disconnect the V
REF−
input from 0 V, load
the DAC with all 0s, and adjust the V
REF−
voltage until V
OUT
= 0 V.
• For gain adjustment, the AD7846 should be loaded with all
1s and R1 adjusted until V
OUT
= 10 (65,535)/(65,536) =
9.999847 V. If a simple resistor divider is used to vary the
V
REF−
voltage, it is important that the temperature
coefficients of these resistors match that of the DAC input
resistance (−300 ppm/°C). Otherwise, extra offset errors are
introduced over temperature. Many circuits do not require
these offset and gain adjustments. In these circuits, R1 can
be omitted. Pin 5 of the AD586 can be left open circuit and
Pin 8 (V
REF−
) of the AD7846 tied to 0 V.
AD7846
Rev. G | Page 14 of 24
BIPOLAR OPERATION
Figure 24 shows the AD7846 set up for ±10 V bipolar operation.
The AD588 provides precision ±5 V tracking outputs that are
fed to the V
REF+
and V
REF−
inputs of the AD7846. The code table
for Figure 24 is shown in Tabl e 9.
DGND
+15
V
+5
V
V
DD
V
SS
V
CC
V
OUT
R
IN
V
REF+
V
REF–
R2
10k
Ω
C1
1µF
SIGNAL
GROUND
–15V
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7846*
AD588
V
OUT
(–10V TO +10V)
+15V
–15V
R3
100kΩ
R1
39kΩ
+15
V
4
21
9
5
6
20
7
2
3
1
14
15
16
13812
11
10
5
9
7
46
8
0
8490-024
Figure 24. Bipolar ±10 V Operation
Table 9. Offset Binary Code Table for Figure 24
Binary Number in DAC Latch
MSB LSB
1
Analog Output (V
OUT
)
1111 1111 1111 1111 +10 (32,767/32,768) V
1000 0000 0000 0001 +10 (1/32,768) V
1000 0000 0000 0000 0 V
0111 1111 1111 1111 −10 (1/32,768) V
0000 0000 0000 0000 −10 (32,768/32,768) V
1
LSB = 10 V/2
15
= 10 V/32,768 = 305 V.
Full-scale and bipolar zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and −5 V outputs together
with respect to ground.
For bipolar zero adjustment on the AD7846, load the DAC with
100…000 and adjust R3 until V
OUT
= 0 V. Full scale is adjusted
by loading the DAC with all 1s and adjusting R2 until V
OUT
=
9.999694 V.
When bipolar zero and full-scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be connected
to Pin 11, and Pin 5 should be left floating. If a user wants a 5 V
output range, there are two choices. By tying Pin 6 (R
IN
) of the
AD7846 to V
OUT
(Pin 5), the output stage gain is reduced to
unity and the output range is ±5 V. If only a positive 5 V reference
is available, bipolar ±5 V operation is still possible. Tie V
REF−
to
0 V and connect R
IN
to V
REF+
. This also gives a ±5 V output
range. However, the linearity, gain, and offset error specifications
are the same as the unipolar 0 V to 5 V range.
MULTIPLYING OPERATION
The AD7846 is a full multiplying DAC. To obtain four-quadrant
multiplication, tie V
REF−
to 0 V, apply the ac input to V
REF+
, and
tie R
IN
to V
REF+
. Figure 11 shows the large signal frequency
response when the DAC is used in this fashion.
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AD7846JP

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Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-Bit VOut CMOS
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