74SSTVF16859NLG Datasheet 74FCT240ATSOG, 74FCT240ATPYG, 74FCT240CTPYG | P4-P6

COMMERCIAL TEMPERATURE RANGE

IDT74SSTVF16859

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VIK Control Inputs VDD = 2.5V, II= −18mA — — –1.2 V

VOH VDD = 2.5V to 2.7V, IOH = -100μAVDD – 0.2 — — V

VDD = 2.5V, IOH = -8mA 1.95 — —

OL VDD = 2.5V to 2.7V, IOL = 100μA — — 0.2 V

VDD = 2.5V, IOL = 8mA — — 0.35

II All Inputs VDD = 2.7V,VI = VDD or GND — — ±5 μA

DD Static Standby IO = 0, VDD = 2.7V, RESET = GND — — 0.01 mA

Static Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC) ——20

Dynamic Operating (Clock Only) I

O = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—6—μA/Clock

CLK and CLK Switching 50% Duty Cycle. MHz

IDDD Dynamic Operating IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),—43—μA/Clock

(Per Each Data Input)

(1)

CLK and CLK Switching 50% Duty Cycle. One Data Input MHz/Data

Switching at Half Clock Frequency, 50% Duty Cycle. Input

Data Inputs VDD = 2.6V, VI = VREF ± 310mV 2 — 3

I CLK and CLK VICR = 1.3V, VI (PP) = 360mV 2 — 3 pF

RESET V

I = VDD or GND 2 — 3

NOTE:

1. Power dissipation levels will allow operation at DDR400 speeds without excessive die temperature.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = 0°C to +70°C, VDD = 2.6V ±0.1V, VDDQ = 2.6V ±0.1V

OPERATING CHARACTERISTICS, TA = 25ºC

(1)

Symbol Parameter Min. Typ.

(1)

Max. Unit

VDD Supply Voltage VDDQ — 2.7 V

VDDQ Output Supply Voltage PC1600-PC2700 2.3 2.5 2.7 V

PC3200 2.5 2.6 2.7

REF Reference Voltage (VREF= VDDQ/2) PC1600-PC2700 1.15 1.25 1.35 V

PC3200 1.25 1.3 1.35

VTT Termination Voltage VREF– 40mV VREF VREF+ 40mV V

VI Input Voltage 0 — VDD V

VIH AC High-Level Input Voltage Data Inputs VREF+ 310mV — — V

VIL AC Low-Level Input Voltage Data Inputs — — VREF– 310mV V

VIH DC High-Level Input Voltage Data Inputs VREF+ 150mV — — V

VIL DC Low-Level Input Voltage Data Inputs — — VREF– 150mV V

VIH High-Level Input Voltage RESET 1.7 — — V

VIL Low-Level Input Voltage RESET — — 0.7 V

VICR Common-Mode Input Range CLK, CLK 0.97 — 1.53 V

VI (PP) Peak-to-Peak Input Voltage CLK, CLK 360 — — mV

IOH High-Level Output Current — — – 16 mA

IOL Low-Level Output Current — — 16

A Operating Free-Air Temperature 0 — +70 ° C

NOTE:

1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.

COMMERCIAL TEMPERATURE RANGE

IDT74SSTVF16859

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR

TEMPERATURE RANGE

PC1600 - PC2700 PC3200

Symbol Parameter Min. Max. Min. Max. Unit

CLOCK Clock Frequency — 200 — 220 MHz

tw Pulse Duration, CLK, CLK HIGH or LOW 2.5 — 2.5 — ns

tACT Differential Inputs Active Time

(1)

—22—22ns

tINACT Differential Inputs Inactive Time

(2)

—22—22ns

tSU Setup Time, Fast Slew Rate

(3, 5)

Data Before CLK↑, CLK↓ 0.65 — 0.65 — ns

Setup Time, Slow Slew Rate

(4, 5)

0.75 — 0.75 — ns

tH Hold Time, Fast Slew Rate

(3,5)

Data Before CLK↑, CLK ↓ 0.75 — 0.65 — ns

Hold Time, Slow Slew Rate

(2,5)

0.9 — 0.8 — ns

SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING

RANGE (UNLESS OTHERWISE NOTED)

PC1600 - PC2700 PC3200

Symbol Parameter Min. Max. Min. Max. Unit

fMAX 200 — 220 — MH z

tPDM CLK and CLK to Q 1.1 2.6 1.1 2.4 ns

tPDMSS CLK and CLK to Q (simultaneous switching) — 2.9 — 2.68 ns

PHL RESET to Q — 5 — 5 ns

NOTES:

1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.

2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.

3. For data signal input slew rate is ≥1V/ns.

4. For data signal input slew rate is ≥0.5V/ns and <1V/ns.

5. CLK, CLK signal input slew rates are ≥1V/ns.

COMMERCIAL TEMPERATURE RANGE

IDT74SSTVF16859

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

TEST CIRCUITS AND WAVEFORMS

FOR PC1600 - PC2700, V

DD = 2.5V ± 0.2V

FOR PC3200, VDD = 2.6V ± 0.1V

Voltage Waveforms - Pulse Duration

NOTES:

1. CL includes probe and jig capacitance.

2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.

3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. VTT = VREF = VDDQ/2

6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.

7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.

8. tPDM is tPD with one output switching. tPDMSS is tPD with all outputs switching.

Load Circuit

Voltage Waveforms - Setup and Hold Times

Voltage Waveforms - Propagation Delay Times

Voltage and Current Waveforms

Inputs Active and Inactive Times

Timing

Input

ICR

VI(PP)

tPLH tPH L

Output

VOL

VICR

VTT VTT

VOH

VOL

VIH

VIL

tPHL

VDD/2

LVCMOS

RESET

Input

Output

VREF

VIH

VIL

VRE F

Input

VREF

VIH

VIL

VREF

Input

VICR VI(PP)

tSU tH

Timing

Input

From output

under test

Test Point

LVCMOS

RESET

Input

DD/2

tINACT tACT

IDD

VDD/2

90%

(see note 2)

10%

VTT

CL =30pF

(see note 1)

RL =50Ω

P1-P3 P4-P6 P7-P7

74SSTVF16859NLG

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Registers 13TO26BIT REG BUFFER SSTL

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74SSTVF16859NLG

74SSTVF16859NLG

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