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89H48H12AG2ZCBL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
4 of 59 December 12, 2013
IDT 89HPES48H12AG2 Datasheet
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Figure 3 Split SMBus Interface Configuration
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
Hot-Plug Interface
The PES48H12AG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES48H12AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12AG2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12AG2. In response to an I/O expander interrupt, the PES48H12AG2 generates
an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1 SSMBADDR[1] MSMBADDR[1]
2 SSMBADDR[2] MSMBADDR[2]
3 SSMBADDR[3] MSMBADDR[3]
4 0 MSMBADDR[4]
5 SSMBADDR[5] 1
61 0
71 1
Table 1 Master and Slave SMBus Address Assignment
Processor
Switch
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
Hot-Plug
I/O
Expander
5 of 59 December 12, 2013
IDT 89HPES48H12AG2 Datasheet
General Purpose Input/Output
The PES48H12AG2 provides 54 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES48H12AG2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal Type Name/Description
PE00RP[3:0]
PE00RN[3:0]
I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE00TP[3:0]
PE00TN[3:0]
O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PE01RP[3:0]
PE01RN[3:0]
I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PE01TP[3:0]
PE01TN[3:0]
O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PE02RP[3:0]
PE02RN[3:0]
I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE02TP[3:0]
PE02TN[3:0]
O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE03RP[3:0]
PE03RN[3:0]
I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PE03TP[3:0]
PE03TN[3:0]
O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PE04RP[3:0]
PE04RN[3:0]
I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE04TP[3:0]
PE04TN[3:0]
O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PE05RP[3:0]
PE05RN[3:0]
I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PE05TP[3:0]
PE05TN[3:0]
O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PE06RP[3:0]
PE06RN[3:0]
I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE06TP[3:0]
PE06TN[3:0]
O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
Table 2 PCI Express Interface Pins (Part 1 of 2)
6 of 59 December 12, 2013
IDT 89HPES48H12AG2 Datasheet
PE07RP[3:0]
PE07RN[3:0]
I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.
PE07TP[3:0]
PE07TN[3:0]
O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
PE08RP[3:0]
PE08RN[3:0]
I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive
pairs for port 8.
PE08TP[3:0]
PE08TN[3:0]
O PCI Express Port 8 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 8.
PE09RP[3:0]
PE09RN[3:0]
I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive
pairs for port 9. When port 8 is merged with port 9, these signals become
port 8 receive pairs for lanes 4 through 7.
PE09TP[3:0]
PE09TN[3:0]
O PCI Express Port 9 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 9. When port 8 is merged with port 9, these signals
become port 8 transmit pairs for lanes 4 through 7.
PE10RP[3:0]
PE10RN[3:0]
I PCI Express Port 10 Serial Data Receive. Differential PCI Express
receive pairs for port 10.
PE10TP[3:0]
PE10TN[3:0]
O PCI Express Port 10 Serial Data Transmit. Differential PCI Express
transmit pairs for port 10.
PE11RP[3:0]
PE11RN[3:0]
I PCI Express Port 11 Serial Data Receive. Differential PCI Express
receive pairs for port 11. When port 10 is merged with port 11, these sig-
nals become port 10 receive pairs for lanes 4 through 7.
PE11TP[3:0]
PE11TN[3:0]
O PCI Express Port 11 Serial Data Transmit. Differential PCI Express
transmit pairs for port 11. When port 10 is merged with port 11, these sig-
nals become port 10 transmit pairs for lanes 4 through 7.
Signal Type Name/Description
GCLKN[1:0]
GCLKP[1:0]
I Global Reference Clock. Differential reference clock input pair. This clock
is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
P[11:0]CLKN
P[11:0]CLKP
I Port [11:0] Reference Clocks. Differential reference clock pairs associated
with ports.
Table 3 Reference Clock Pins
Signal Type Name/Description
MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 4 SMBus Interface Pins (Part 1 of 2)
Signal Type Name/Description
Table 2 PCI Express Interface Pins (Part 2 of 2)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

89H48H12AG2ZCBL

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Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
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