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LTC5542IUH#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC5542
13
5542f
APPLICATIONS INFORMATION
Bandpass IF Matching
The IF output can be matched for IF frequencies as low
as 90MHz or as high as 500MHz using the bandpass
IF matching shown in Figure 1 and Figure 7. L1 and L2
resonate with the internal IF output capacitance at the
desired IF frequency. The value of L1, L2 is calculated
as follows:
L1, L2 = 1/[(2 π f
IF
)
2
• 2 • C
IF
]
where C
IF
is the internal IF capacitance (listed in Table 4).
Values of L1 and L2 are tabulated in Figure 1 for various IF
frequencies. For IF frequencies below 90MHz, the values
of L1, L2 become unreasonably high and the lowpass
topology shown in Figure 9 is preferred. Measured IF
output return loss for bandpass IF matching is plotted
in Figure 10.
Table 4. IF Output Impedance vs Frequency
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT
IMPEDANCE (R
IF
|| X
IF
(C
IF
))
90 320 || –j842 (2.1pF)
140 312 || –j541 (2.1pF)
190 300 || –j419 (2.0pF)
240 294 || –j301 (2.2pF)
300 287 || –j221 (2.4pF)
380 280 || –j161 (2.6pF)
500 269 || –j120 (2.65pF)
Lowpass IF Matching
An alternative IF matching network shown in Figure 9 uses
a lowpass topology, which provides excellent RF to IF
and LO to IF isolation. V
CCIF
is supplied through the center
tap of the 4:1 transformer. A 250 to 200 lowpass
impedance transformation is realized by shunt elements
R2 and C13 (in parallel with the internal R
IF
and C
IF
),
and series inductors L1 and L2. Resistor R2 is selected
to reduce the IF output resistance to 250, or it can be
deleted for the highest conversion gain. The fi nal impedance
transformation to 50 is realized by transformer T1. The
matching element values shown in Figure 9 are optimized
for a wideband 30MHz to 150MHz IF match.The demo
board (see Figure 2) has been laid out to accommodate
this matching topology with very few modifi cations.
IF Amplifi er Bias
The IF amplifi er delivers excellent performance with
V
CCIF
= 3.3V, which allows the V
CC
and V
CCIF
supplies
to be common. With V
CCIF
increased to 5V, the RF input
P1dB increases by more than 3dB, at the expense of higher
power consumption. Mixer performance at 2400MHz is
shown in Table 5 with V
CCIF
= 3.3V and 5V. For the highest
conversion gain, high-Q wire-wound chip inductors are
recommended for L1 and L2, especially when using
V
CCIF
= 3.3V. Low-cost multilayer chip inductors may be
substituted, with a slight reduction in conversion gain.
4:1
T1
IF
OUT
50
V
CCIF
3.1-5.3V
C8
22pF
1819
IF
–
IF
+
C9
1µF
C13
1.5pF
R2
1k
L1
82nH
L2
82nH
LTC5542
5542 F09
Figure 9. IF Output with Lowpass Matching
FREQUENCY (MHz)
50
–25
RETURN LOSS (dB)
–10
–5
–15
–20
0
100 400 450 500 550150 200 250 300
5542 F10
350
270nH
150nH
100nH
33nH
Figure 10. IF Output Return Loss - Bandpass Matching
LTC5542
14
5542f
APPLICATIONS INFORMATION
Table 5. Performance Comparison with V
CCIF
= 3.3V and 5V
(RF = 2400MHz, Low-Side LO, IF = 190MHz)
V
CCIF
I
CCIF
(mA)
G
C
(dB)
P1dB
(dBm)
IIP3
(dBm)
NF
(dB)
3.3V 100 8.0 11.3 26.8 9.9
5V 103 7.9 14.7 27.3 10.0
The IFBIAS pin (pin 20) is available for reducing the DC
current consumption of the IF amplifi er, at the expense of
IIP3. This pin should be left open-circuited for optimum
performance. The internal bias circuit produces a 4mA
reference for the IF amplifi er, which causes the amplifi er
to draw approximately 100mA. If resistor R1 is connected
to pin 20 as shown in Figure 7, a portion of the reference
current can be shunted to ground, resulting in reduced
IF amplifi er current. For example, R1 = 1k will shunt
away 1.5mA from pin 20 and the IF amplifi er current will
be reduced by 38% to approximately 62mA. The nominal,
open-circuit DC voltage at pin 20 is 2.1V. Table 6 lists RF
performance versus IF amplifi er current.
Table 6. Mixer Performance with Reduced IF Amplifi er Current
(RF = 2400MHz, Low-Side LO, IF = 190MHz, V
CC
= V
CCIF
= 3.3V)
R1
(kΩ)
I
CCIF
(mA)
G
C
(dB)
IIP3
(dBm)
P1dB
(dBm)
NF
(dB)
OPEN 100 8.0 26.8 11.3 9.9
4.7 90 7.7 26.3 11.4 9.9
2.2 81 7.4 25.4 11.6 9.9
1 62 6.9 23.4 11.6 10.0
(RF = 1950MHz, High-Side LO, IF = 190MHz
, V
CC
= V
CCIF
= 3.3V)
R1
(kΩ)
I
CCIF
(mA)
G
C
(dB)
IIP3
(dBm)
P1dB
(dBm)
NF
(dB)
OPEN 100 8.5 25.2 11.0 9.4
4.7 90 8.3 24.9 11.1 9.3
2.2 81 8.0 24.3 11.3 9.3
1 62 7.6 22.8 11.3 9.4
LTC5542
5
SHDN
500
V
CC2
5542 F11
6
Figure 11. Shutdown Input Circuit
Shutdown Interface
Figure 11 shows a simplifi ed schematic of the SHDN pin
interface. To disable the chip, the SHDN voltage must be
higher than 3.0V. If the shutdown function is not required,
the SHDN pin should be connected directly to GND. The
voltage at the SHDN pin should never exceed the power
supply voltage (V
CC
) by more than 0.3V. If this should
occur, the supply current could be sourced through the
ESD diode, potentially damaging the IC.
The SHDN pin must be pulled high or low. If left fl oating,
then the on/off state of the IC will be indeterminate. If a
three-state condition can exist at the SHDN pin, then a
pull-up or pull-down resistor must be used.
Supply Voltage Ramping
Fast ramping of the supply voltage can cause a current
glitch in the internal ESD protection circuits. Depending on
the supply inductance, this could result in a supply voltage
transient that exceeds the maximum rating. A supply voltage
ramp time of greater than 1ms is recommended.
LTC5542
15
5542f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
5.00 p 0.10
5.00 p 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.60 REF
2.70 p 0.10
0.75 p 0.05
R = 0.125
TYP
R = 0.05
TYP
0.25 p 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
(UH20) QFN 0208 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 p0.05
0.25 p0.05
0.65 BSC
2.60 REF
2.70 p 0.05
4.10 p 0.05
5.50 p 0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 s 45o
CHAMFER
2.70 p 0.10
2.70 p 0.05
UH Package
20-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1818 Rev Ø)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC5542IUH#PBF

Mfr. #:
Buy LTC5542IUH#PBF
Manufacturer:
Analog Devices Inc.
Description:
RF Mixer 1.6GHz - 2.7GHz High Dynamic Range Downconverting Mixer
Lifecycle:
New from this manufacturer.
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