CS3310-KSZ Datasheet CS3310-KSZ, CS3310-KSZR, CDB3310 | P7-P9

CS3310

DS82F1 7

In single device operation, volume control data is loaded into the 16-bit shift register by holding

the CS pin low for sixteen SCLK pulses and then latched on the rising edge of CS. The previous

contents of the shift-register are shifted through the register and out SDATAO during the process.

Multi-channel operation can be implemented as shown in Figure 4 by connecting the SDATAO

of device #1 to the SDATAI pin of device #2. In this manner multiple CS3310s can be loaded from

a single serial data line without complex addressing schemes. Volume control data is loaded by

holding CS low for 16 x N SCLK pulses, where N is the number of devices in the chain. The 16

bits clocked into device #1 on SCLK pulses 1-16 are clocked into device #2 on SCLK pulses 17-

32. The CS3310s are simultaneously updated on the rising edge of CS following 16 x N SCLK

pulses Notice that a 47 kohm resistor is required to terminate SDATAI, as shown in Figure 4, due

to the high impedance state of SDATAO when CS is high..

R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0

SCLK

SDATAI

SDATAO

L0 = Left Channel Least Significant Bit R0 = Right Channel Least Significant Bit

L7 = Left Channel Most Significant Bit R7 = Right Channel Most Significant Bit

SDATAI is latched internally on the rising edge of SCLK

SDATAO transitions after the falling edge of SCLK

SDATAO bits reflect the data previously loaded into the CS3310

Figure 3. Serial Port Timing

AUDIO

SIGNAL

AINL

AINR

SDATAI

SDATAO

AOUTL

AOUTR

SCLK

CS3310

CONTROLLER

AUDIO

SIGNAL

AINL

AINR

SDATAI

SDATAO

AOUTL

AOUTR

SCLK

CS3310

47 k

Figure 4. Daisy Chaining Diagram

CS3310

8 DS82F1

Changing the Analog Output Level

Care has been taken to ensure that there are no audible artifacts in the analog output signal dur-

ing volume control changes. The gain/attenuation changes of the CS3310 occur at zero cross-

ings to eliminate glitches during level transitions. The zero crossing for the left channel is the

voltage potential at the AGNDL pin; the voltage potential at the AGNDR pin defines the right

channel zero crossing.

A volume control change occurs after chip select latches the data in the volume control data reg-

ister and two zero crossings are detected. If two zero crossings are not detected within 18 ms of

the change in CS, the new volume setting is implemented. The zero crossing enable pin, ZCEN,

enables or disables the zero crossing detection function as well as the 18 ms time-out circuit.

Analog Inputs and Outputs

The maximum input level is limited by the common-mode voltage capabilities of the internal op-

amp. Signals approaching the analog supply voltages may be applied to the AIN pins if the inter-

nal attenuator limits the output signal to within 1.25 volts of the analog supply rails.

The outputs are capable of driving 600 Ω loads to within 1.25 volts of the analog supply rails and

are short circuit protected to 20 mA.

As with any adjustable gain stage the affects of a DC offset at the input must be considered. Ca-

pacitively coupling the analog inputs may be required to prevent “clicks and pops” which occur

with gain changes if an appreciable offset is present.

Source Impedance Requirements

The CS3310 requires a low source impedance to achieve maximum performance. The ESD pro-

tection diodes on the analog input pins are reversed biased during normal operation. A charac-

teristic of a reversed biased diode is a non-linear voltage dependent capacitance which can be

Input Code

(Left or Right Channel) Gain or Attenuation (dB)

11111111

11111110

•

11000000

•

00000010

00000001

00000000

+31.5

+31.0

•

-95.0

-95.5

Software Mute

Table 1. Input Code Definition

CS3310

DS82F1 9

a source of distortion if the source impedance becomes appreciable relative to the reversed bi-

ased diode capacitance. Source impedances equal to or less than 600 ohms will avoid this dis-

tortion mechanism for the CS3310.

Mute

Muting can be achieved by either hardware or software control. Hardware muting is accom-

plished via the MUTE input and software muting by loading all zeroes into the volume control reg-

ister.

MUTE disconnects the internal buffer amplifiers from the output pins and terminates AOUTL and

AOUTR with 10 kΩ resistors to ground. The mute is activated with a zero crossing detection (in-

dependent of the zero cross enable status) or an 18 ms timeout to eliminate any audible “clicks”

or “pops”. MUTE also initiates an internal offset calibration.

A software mute is implemented by loading all zeroes into the volume control register. The inter-

nal amplifier is set to unity gain with the amplifier input connected to the maximum attenuation

point of the resistive divider, AGND.

A “soft mute” can be accomplished by sequentially ramping down from the current volume control

setting to the maximum attenuation code of all zeroes.

Power-Up Considerations

Upon initial application of power, the MUTE pin of the CS3310 should be set low to initiate a pow-

er-up sequence. This sequence sets the serial shift register and the volume control register to

zero and performs an offset calibration. The device should remain muted until the supply voltag-

es have settled to ensure an accurate calibration. The device also includes an internal power-on

reset circuit that requires approximately 100 µs to settle and will ignore any attempts to address

the internal registers during this period.

The offset calibration minimizes internally generated offsets and ignores offsets applied to the

AIN pins. External clocks are not required for calibration.

Although the device is tolerant to power supply variation, the device will enter a hardware mute

state if the power supply voltage drops below approximately ±3.5 volts. A power-up sequence

will be initiated if the power supply voltage returns to greater than ±3.5 volts.

Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the

recommended power connections.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

CS3310-KSZ

Mfr. #:

Buy CS3310-KSZ

Manufacturer:

Cirrus Logic

Description:

Audio Amplifiers Stereo Digital Volume Control

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CS3310-KSZ

CS3310-KSZ

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