9FG104EGLFT Datasheet 9FG104EGLFT, 9FG104EGILFT, 9FG104EFLFT | P10-P12

ICS9FG104E

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA

IDT®

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 10

ICS9FG104E REV D 102912

SMBus Table: Reserved Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Reserved Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: M/N Programming Enable

Pin # Name Control Function Type 0 1 Default

Bit 7

M/N_Enable M/N Prog. Enable RW Disable Enable 0

Bit 6

Bit 5

REFOUT_En REFOUT Enable RW Disable Enable 1

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: PLL Frequency Control Register

Pin # Name Control Function Type 0 1 Default

Bit 7

PLL N Div8 N Divider Prog bit 8 RW X

Bit 6

PLL N Div9 N Divider Prog bit 9 RW X

Bit 5

PLL M Div5 RW X

Bit 4

PLL M Div4 RW X

Bit 3

PLL M Div3 RW X

Bit 2

PLL M Div2 RW X

Bit 1

PLL M Div1 RW X

Bit 0

PLL M Div0 RW X

Byte 10

The decimal representation

of M and N Divider in Byte

11 and 12 will configure the

PLL VCO frequency. Default

at power up = latch-in or

Byte 0 Rom table. VCO

Frequency = fXTAL x

[NDiv(9:0)+8] / [MDiv(5:0)+2]

M Divider Programming

bit (5:0)

- Reserved

Reserved

- Reserved

Reserved

- Reserved

Reserved

Byte 9

Byte 8

Byte 7

Reserved

Reserved-

Reserved

ICS9FG104E

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA

IDT®

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 11

ICS9FG104E REV D 102912

SMBus Table: PLL Frequency Control Register

Pin # Name Control Function Type 0 1 Default

Bit 7

PLL N Div7 RW X

Bit 6

PLL N Div6 RW X

Bit 5

PLL N Div5 RW X

Bit 4

PLL N Div4 RW X

Bit 3

PLL N Div3 RW X

Bit 2

PLL N Div2 RW X

Bit 1

PLL N Div1 RW X

Bit 0

PLL N Div0 RW X

SMBus Table: PLL Spread Spectrum Control Register

Pin # Name Control Function Type 0 1 Default

Bit 7

PLL SSP7 RW X

Bit 6

PLL SSP6 RW X

Bit 5

PLL SSP5 RW X

Bit 4

PLL SSP4 RW X

Bit 3

PLL SSP3 RW X

Bit 2

PLL SSP2 RW X

Bit 1

PLL SSP1 RW X

Bit 0

PLL SSP0 RW X

SMBus Table: PLL Spread Spectrum Control Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

PLL SSP14 RW X

Bit 5

PLL SSP13 RW X

Bit 4

PLL SSP12 RW X

Bit 3

PLL SSP11 RW X

Bit 2

PLL SSP10 RW X

Bit 1

PLL SSP9 RW X

Bit 0

PLL SSP8 RW X

SMBus Table: Reserved Test Register

Pin # Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved Test Register. Do not write to this register, erratic device operation may

occur.

Reserved

Spread Spectrum

Programming bit(14:8)

These Spread Spectrum bits

in Byte 13 and 14 will

program the spread

pecentage of PLL

Byte 13

Byte 14

Byte 12

These Spread Spectrum bits

in Byte 13 and 14 will

program the spread

pecentage of PLL

Spread Spectrum

Programming bit(7:0)

Byte 11

N Divider Programming

Byte11 bit(7:0) and

Byte10 bit(7:6)

The decimal representation

of M and N Divider in Byte

11 and 12 will configure the

PLL VCO frequency. Default

at power up = latch-in or

Byte 0 Rom table. VCO

Frequency = fXTAL x

[NDiv(9:0)+8] / [MDiv(5:0)+2]

ICS9FG104E

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA

IDT®

FREQUENCY GENERATOR FOR PCIE GEN1/2, USB3.0, QPI & SATA 12

ICS9FG104E REV D 102912

DIF_STOP# - Assertion (transition from '1' to '0')

Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus

DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =

HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is

programmed to a '1', DIF outputs will be tri-stated.

DIF_STOP# - De-assertion (transition from '0' to '1')

With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the

de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of

interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a

voltage greater than 200mV.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

9FG104EGLFT

Mfr. #:

Buy 9FG104EGLFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner 4 O/P PCIE GEN2 SYNTHESIZER

Lifecycle:

New from this manufacturer.

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9FG104EGLFT

9FG104EGLFT

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