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74HC2G00DC,125

P1-P3P4-P6P7-P9P10-P12P13-P15
74HC_HCT2G00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 26 September 2013 9 of 14
NXP Semiconductors 74HC2G00; 74HCT2G00
Dual 2-input NAND gate
Fig 9. Package outline SOT765-1 (VSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(2)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187
02-06-07
w M
b
p
D
Z
e
0.12
14
8
5
θ
A
2
A
1
Q
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index
74HC_HCT2G00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 26 September 2013 10 of 14
NXP Semiconductors 74HC2G00; 74HCT2G00
Dual 2-input NAND gate
Fig 10. Package outline SOT996-2 (XSON8)
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT996-2
sot996-2_po
07-12-21
12-11-20
Unit
(1)
mm
max
nom
min
0.5
0.05
0.00
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
0.5 1.5
0.05
A
Dimensions (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
A
1
b
0.35
0.15
DEee
1
LL
1
L
2
v
0.1
wy
0.05
y
1
0.1
0 1 2 mm
scale
C
y
C
y
1
X
terminal 1
index area
B A
D
E
detail X
A
A
1
b
14
85
e
1
e
AC
B
v
Cw
L
2
L
1
L
74HC_HCT2G00 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 26 September 2013 11 of 14
NXP Semiconductors 74HC2G00; 74HCT2G00
Dual 2-input NAND gate
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT2G00 v.5 20130926 Product data sheet - 74HC_HCT2G00 v.4
Modifications:
• For type numbers 74HC2G00GD and 74HCT2G00GD XSON8U has changed to XSON8.
74HC_HCT2G00 v.4 20080703 Product data sheet - 74HC_HCT2G00 v.3
74HC_HCT2G00 v.3 20060405 Product data sheet - 74HC_HCT2G00 v.2
74HC_HCT2G00 v.2 20030212 Product specification - 74HC_HCT2G00 v.1
74HC_HCT2G00 v.1 20020710 Product specification - -
P1-P3P4-P6P7-P9P10-P12P13-P15

74HC2G00DC,125

Mfr. #:
Buy 74HC2G00DC,125
Manufacturer:
Nexperia
Description:
Logic Gates DUAL 2-INPUT NAND
Lifecycle:
New from this manufacturer.
Delivery:
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