22
COMMERCIAL TEMPERATURE RANGE
IDT72V3624/72V3644 3.3V CMOS SyncBiFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 1,024 x 36 x 2
EFB/ORB
MBB
CSB
W/RB
ENB
CLKB
HIGH
B0-B8
B0-B8
Read 5
Read 2 Read 3
Read 4
Read 3
Read 4
Previous Data
Read 2
No Operation
t
DIS
t
DIS
t
A
t
A
t
A
t
A
t
A
t
A
t
ENS2
t
ENH
t
A
t
A
Read 1
(Standard Mode)
(FWFT Mode)
t
EN
t
MDV
t
MDV
t
EN
OR
Read 1
4664 drw15
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE
(1)
DATA WRITTEN TO FIFO1 READ DATA READ
NO. FROM FIFO1
BM SIZE BE A35-A27 A26-A18 A17-A9 A8-A0 B8-B0
HHH ABCD
HH L ABCD
1A
2B
3C
4D
1D
2C
3B
4A
NOTE:
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.
NOTE:
1. Read From FIFO2.
4664 drw16
CLKA
EFA/ORA
ENA
MBA
CSA
W/RA
t
CLK
t
CLKH
t
CLKL
t
A
t
MDV
t
EN
tA
t
ENH
t
ENH
W1
W2
W3
(1)
(1)
t
ENH
t
DIS
No Operation
A0-A35
(FWFT Mode)
t
EN
W2
(1)
(1)
t
DIS
W1
Previous Data
A0-A35
(Standard Mode)
t
MDV
t
A
OR
t
A
HIGH
t
ENS2
t
ENS2
t
ENS2
(1)
