Philips Semiconductors Product specification
PCK2001M
14.318–150 MHz I
2
C 1:10 clock buffer
2000 May 17
10
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: Output active/inactive register
1 = enable; 0 = disable
BIT
PIN# NAME DESCRIPTION
7 BUF_OUT7 Initialize to 0
6 BUF_OUT6 Initialize to 0
5 BUF_OUT5 Initialize to 0
4 BUF_OUT4 Initialize to 0
3 7 BUF_OUT3 Active/Inactive
2 6 BUF_OUT2 Active/Inactive
1 3 BUF_OUT1 Active/Inactive
0 2 BUF_OUT0 Active/Inactive
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 1: Output active/inactive register
1 = enable; 0 = disable
BIT
PIN# NAME DESCRIPTION
7 27 BUF_OUT15 Active/Inactive
6 26 BUF_OUT14 Active/Inactive
5 23 BUF_OUT13 Active/Inactive
4 22 BUF_OUT12 Active/Inactive
3 BUF_OUT11 Initialize to 0
2 BUF_OUT10 Initialize to 0
1 BUF_OUT9 Initialize to 0
0 BUF_OUT8 Initialize to 0
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 2: Optional register for possible future requirments
BIT PIN# NAME DESCRIPTION
7 18 BUF_OUT17 Active/Inactive
6 11 BUF_OUT16 Active/Inactive
5 (reserved) (reserved)
4 (reserved) (reserved)
3 (reserved) (reserved)
2 (reserved) (reserved)
1 (reserved) (reserved)
0 (reserved) (reserved)
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Philips Semiconductors Product specification
PCK2001M
14.318–150 MHz I
2
C 1:10 clock buffer
2000 May 17
11
AC WAVEFORMS
V
M
= 1.5 V
V
X
= V
OL
+ 0.3 V
V
Y
= V
OH
–0.3 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
BUF_IN
INPUT
V
M
t
PLH
t
PHL
BUF_OUT
V
M
V
M
V
M
SW00246
V
DD
Figure 1. Load circuitry for switching times.
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00245
V
DD
Figure 2. 3-State enable and disable times
DUTY CYCLE
T
SDKP
T
SDKH
T
SDRISE
T
SDFALL
T
SDKL
2.4
1.5
0.4
SW00247
Figure 3. SDRAM Output clock
DUTY CYCLE
t
kp
t
kh
t
r
t
f
t
kl
2.4
1.5
0.4
SW00479
Figure 4. Buffer Output clock
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
V
DD
TEST S
1
t
PLH
/t
PHL
Open
t
PLZ
/t
PZL
2<V
DD
t
PHZ
/t
PZH
V
SS
Open
V
SS
S
1
2<V
DD
500
500
SW00251
Figure 5. Load circuitry for switching times
14.318-150 MHz I
2
C 1:10 clock buffer
Philips Semiconductors Product specification
PCK2001M
2000 May 17
12
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm SOT341-1

PCK2001MDB,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 1:10 150MHZ 28SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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