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LT3473EDD#PBF

P1-P3P4-P6P7-P9P10-P12
10
LT3473/LT3473A
3473f
between the OUT pin and ground. A ceramic capacitor with
a value of 1µF is a good choice. The voltage drop (PNP
V
CESAT
) can be accounted for by setting the output voltage
according to the following formula:
VVV V
R
R
V
OUT INT CESAT REF CESAT
==+
⎛
⎝
⎜
⎞
⎠
⎟
–•–1
2
1
Auxiliary NPN Devices (LT3473A Only)
The LT3473A has two auxiliary NPNs as shown in the
Block Diagram that can provide intermediate outputs less
than OUT. The collectors of the NPNs are connected to the
OUT pin internally. Each NPN can dissipate 100mW safely
and has a minimum beta of 60. A resistor string can be
APPLICATIO S I FOR ATIO
WUUU
2
4
R
EXT1
R
EXT2
R
EXT3
NE1
3
NB1
OUT
6
NE2
5
NB2
3473 F05
Figure 5. Auxiliary NPN Transistors in LT3473A. R
EXT1
, R
EXT2
and R
EXT3
Set Intermediate Voltage at NE1 and NE2
connected to the two bases as shown in Figure 5 to
generate buffered voltage at the emitters. When sourcing
high current at low voltage, keep in mind that the NPNs
will be dissipating a fair amount of power, which must be
supplied by the DC/DC converter.
Thermal Shutdown
The LT3473 has thermal shutdown circuitry that shuts down
the part when the junction temperature reaches approxi-
mately 145°C to protect the part from abnormal operation
with high power dissipation, such as an output short cir-
cuit or excessive power dissipation in the auxiliary NPNs.
The part will turn back on when the junction cools down to
approximately 125°C. If the abnormal condition remains,
the part will turn on and off while maintaining the junction
temperature within the window between 125°C and 145°C.
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW
pin has sharp rise and fall edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. Recommended component place-
ment is shown in Figure 6.
Figure 6. Recommended Component Placement
OUT
1
2
3
4
13
5
6
12
11
10
9
8
7
3473 F06a
OUT
1
2
3
4
9
8
7
6
5
3473 F06b
11
LT3473/LT3473A
3473f
U
PACKAGE DESCRIPTIO
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708)
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
0.25 ± 0.05
3.30 ±0.10
(2 SIDES)
16
127
0.50
BSC
PIN 1
NOTCH
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0603
0.25 ± 0.05
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.70 ±0.05
(2 SIDES)2.20 ±0.05
0.50
BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
12
LT3473/LT3473A
3473f
© LINEAR TECHNOLOGY CORPORATION 2005
LT/TP 0205 1K • PRINTED IN THE USA
PART NUMBER DESCRIPTION COMMENTS
LT1613 550mA (I
SW
), 1.4MHz, High Efficiency Step-Up V
IN
: 0.9V to 10V, V
OUT(MAX)
= 34V, I
Q
= 3mA, I
SD
< 1µA,
DC/DC Converter ThinSOT
TM
Package
LT1615/LT1615-1 300mA/80mA (I
SW
), High Efficiency Step-Up V
IN
: 1V to 15V, V
OUT(MAX)
= 34V, I
Q
= 20µA, I
SD
< 1µA, ThinSOT Package
DC/DC Converter
LT1930/LT1930A 1A (I
SW
), 1.2MHz/2.2MHz, High Efficiency Step-Up V
IN
: 2.6V to 16V, V
OUT(MAX)
= 34V, I
Q
= 4.2mA/5.5mA, I
SD
< 1µA,
DC/DC Converter ThinSOT Package
LT1935 2A (I
SW
), 1.2MHz, High Efficiency Step-Up V
IN
: 2.3V to 16V, V
OUT(MAX)
= 38V, I
Q
= 3mA, I
SD
< 1µA,
DC/DC Converter with Integrated Soft-Start ThinSOT Package
LT1945 Dual Output, Boost/Inverter, 350mA (I
SW
), Constant V
IN
: 1.2V to 15V, V
OUT(MAX)
= ±34V, I
Q
= 40µA, I
SD
< 1µA,
Off-Time, High Efficiency Step-Up DC/DC Converter 10-Lead MS Package
LT1946/LT1946A 1.5A (I
SW
), 1.2MHz/2.7MHz, High Efficiency Step-Up V
IN
: 2.45V to 16V, V
OUT(MAX)
= 34V, I
Q
= 3.2mA, I
SD
< 1µA, MS8 Package
DC/DC Converter
LTC
®
3436 3A (I
SW
), 1MHz, 34V Step-Up DC/DC Converter V
IN
: 3V to 25V, V
OUT(MAX)
= 34V, I
Q
= 0.9mA, I
SD
< 6µA,
TSSOP-16E Package
LT3461/LT3461A 300mA (I
SW
), 1.3MHz/3MHz High Efficiency Step-Up V
IN
: 2.5V to 16V, V
OUT(MAX)
= 38V, I
Q
= 2.8mA, I
SD
< 1µA,
DC/DC Converter with Integrated Schottky Diode ThinSOT Package
LT3463/LT3463A Dual Output, Boost/Inverter, 250mA (I
SW
), Constant V
IN
: 2.3V to 15V, V
OUT(MAX)
= ±40V, I
Q
= 40µA, I
SD
< 1µA, DFN Package
Off-Time, High Efficiency Step-Up DC/DC Converters
with Integrated Schottkys
LT3464 85mA (I
SW
), High Efficiency Step-Up DC/DC Converter V
IN
: 2.3V to 10V, V
OUT(MAX)
= 34V, I
Q
= 25µA, I
SD
< 1µA,
with Integrated Schottky and PNP Disconnect ThinSOT Package
LT3467/LT3467A 1.1A (I
SW
), 1.3MHz/2.1MHz, High Efficiency Step-Up V
IN
: 2.4V to 16V, V
OUT(MAX)
= 40V, I
Q
= 1.2mA, I
SD
< 1µA,
DC/DC Converter with Soft-Start ThinSOT Package
LT3471 Dual Output, Boost/Inverter, 1.3A (I
SW
), 1.2MHz, V
IN
: 2.4V to 16V, V
OUT(MAX)
= ±40V, I
Q
= 2.5mA, I
SD
< 1µA, DFN Package
High Efficiency Boost-Inverting DC/DC Converter
LT3479 3A (I
SW
), 3.5MHz, 42V Step-Up DC/DC Converter V
IN
: 2.5V to 24V, V
OUT(MAX)
= 40V, I
Q
= 5mA, I
SD
< 1µA,
DFN, TSSOP-16E Packages
ThinSOT is a trademark of Linear Technology Corporation.
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO
U
LOAD CURRENT I
O
(mA)
0
EFFICIENCY (%)
70
75
80
80
3473 TA02b
65
60
55
20
40
60
100
V
OUT
= 15V
V
OUT
= 25V
V
IN
= 3.6V
V
OUT
= 20V
C
OUT
2.2µF
V
OUT
25V
80mA
3473 TA02a
100nF
C
IN
4.7µF
C
INT
0.47µF
C
IN
: TAIYO YUDEN JMK107BJ475
C
INT
: TAIYO YUDEN GMK212BJ474
C
OUT
: TAIYO YUDEN GMK325BJ225
L1: TOKO A915AY-6R8M (TYPE D53LC)
V
IN
3V TO 4.2V
2M
100k
LT3473
GND
L1 6.8µH
20k
100k
PGOOD
CTRL
SW
V
IN
SHDN
OUT
CAP
FB
Efficiency
OLED Bias
P1-P3P4-P6P7-P9P10-P12

LT3473EDD#PBF

Mfr. #:
Buy LT3473EDD#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.2A, 1.2MHz Boost DC/DC Converter in DFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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