VS-CPV364M4UPbF
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Vishay Semiconductors
Revision: 25-Oct-17
7
Document Number: 94489
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Fig. 18 - Test Circuit for Measurement of I
LM
, E
on
, E
off(diode)
, t
rr
, Q
rr
,
I
rr
, t
d(on)
, t
r
, t
d(off)
, t
f
Fig. 19 - Test Waveforms for Circuit of Fig. 18a,
Defining E
off
, t
d(off)
, t
f
Fig. 20 - Test Waveforms for Circuit of Fig. 18a,
Defining E
on
, t
d(on)
, t
r
Fig. 21 - Test Waveforms for Circuit of Fig. 18a,
Defining E
rec
, t
rr
, Q
rr
, I
rr
Fig. 18e - Macro Waveforms for Figure 18a’s Test Circuit
Same type
device as
D.U.T.
D.U.T.
430 μF
80 %
of V
CE
t1
Ic
Vce
t1
t2
90% Ic
10% Vce
td(off)
tf
Ic
5% Ic
t1+5µS
Vce ic dt
90% Vge
+Vge
∫
Eoff =
∫
Vce ie dt
t2
t1
5% Vce
Ic
Ipk
Vcc
10% Ic
Vce
t1
t2
DUT VOLTAGE
AND CURRENT
GATE VOLTAGE D.U.T.
+Vg
10% +Vg
90% Ic
tr
td(on)
Eon =
DIODE REVERSE
RECOVERY ENERGY
tx
∫
Erec =
t4
t3
Vd id dt
t4
t3
DIODE RECOVERY
WAVEFORMS
Ic
Vpk
10% Vcc
Irr
10% Irr
Vcc
trr
∫
Qrr =
trr
tx
id dt
Vg
GATE SIGNAL
DEVICE UNDER TES
T
CURRENT D.U.T.
VOLTAGE IN D.U.T.
CURRENT IN D1
t0
t1
t2
