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IP2002TRPBF

P1-P3P4-P6P7-P9P10-P12
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iP2002PbF
Features:
Output current 30A continuous with no derating up to
T
PCB
= 90°C and T
CASE
= 90°C
Operating frequency up to 1MHz
Dual sided heatsink capable
Very small 11mm x 11mm x 2.6mm profile
iP2001PbF footprint compatible
Internal features minimize layout sensitivity *
Optimized for very low power losses
Synchronous Buck
Multiphase Optimized BGA Power Block
Integrated Power Semiconductors, Drivers & Passives
Description
The iP2002PbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.6mm BGA
power block. The only additional components required for a complete multiphase converter are a PWM IC, the
external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component
integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized
internally for layout, heat transfer and component selection.
iP2002PbF Power Block
5/16/06
PD - 97096
* All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no
concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR
Block will function normally without any additional input power supply bypass capacitors. However, for reliable long term operation it is
recommended that at least four 10uF ceramic input decoupling capacitors are provided to the V
IN
pin of each power block. No additional
iP2002PbF Internal Block Diagram
MOSFET
Driver with
dead time
cont rol
V
IN
V
SW
PGND
PRDY
ENABLE
PWM
V
DD
SGND
MOSFET
Driver with
dead time
cont rol
V
IN
V
SW
PGND
PRDY
ENABLE
PWM
V
DD
SGND
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iP2002PbF
All specifications @ 25°C (unless otherwise specified)
Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see
Fig. 8).
Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
Parameter Symbol Min Typ Max Units Conditions
Supply Voltage V
DD
4.6 5.0 5.5 V
Input Voltage Range V
IN
3.0 - 13.2 V see Figs. 2 & 3
Output Voltage Range V
OUT
0.8 - 3.3 V see Figs. 2, 4 & 8
Output Current Range I
OUT
--30 Asee Fig. 2
Operating Frequency fsw 150 - 1000 kHz see Figs. 2 & 5
Operating Duty Cycle D - - 85 %
Recommended Operating Conditions :
Absolute Maximum Ratings :
Electrical Specifications @ V
DD
= 5V (unless otherwise specified) :
Parameter Symbol Min Typ Max Units Conditions
Block Power Loss P
BLK
- 7.2 8.9 W V
IN
= 12V, V
OUT
= 1.3V,
Turn On Delay t
d(on)
-63- I
OUT
= 30A, f
SW
= 1MHz
Turn Off Delay t
d(off)
-26-
V
IN
Quiescent Current I
Q-VIN
- - 1.0 mA Enable = 0V, V
IN
= 12V
V
DD
Quiescent Current I
Q-VDD
--10µA Enable = 0V, V
DD
= 5V
Under-Voltage Lockout UVLO
Start Threshold V
START
4.2 4.4 4.5 V
Hysteresis V
Hys-UVLO
- .05 -
Enable Enable
Input Voltage High V
IH
2.0 - - V
Input Voltage Low V
IL
- - 0.8
Power Ready PRDY
Logic Level High V
OH
4.5 4.6 - V V
DD
= 4.6V, I
Load
= 10mA
Logic Level Low V
OL
- 0.1 0.2 V
DD
< UVLO Threshold, I
Load
= 1mA
PWM Input PWM
Logic Level High V
OH
2.0 - - V
Logic Level Low V
OL
- - 0.8
ns
Parameter Min Typ Max Units Conditions
V
IN
to PGND - - 16 V
V
DD
to SGND - - 6.0 V
PWM to SGND -0.3 - V
DD
+0.3 V not to exceed 6.0V
Enable to SGND -0.3 - V
DD
+0.3 V not to exceed 6.0V
Output RMS Current - - 30 A
Block Temperature -40 - 125 °C
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iP2002PbF
Pin Description Table
Pin Name Ball Designator Pin Function
V
DD
A1 – A3, B1 – B3
Supply voltage for the internal circuitry.
V
IN
A5 – A12, B5 – B12,
C5 - C10
Input voltage for the DC-DC converter.
PGND
C11, C12, D11, D12, E11,
E12, F6, F7, F12, G6, G7,
G12, H6, H7, H12, J6, J7, J12,
K5 – K7, K12, L5, L6, L12,
M5 – M7, M12
Power Ground - connection to the ground of
bulk and filter capacitors.
V
SW
D5 – D10, E5 – E10,
F8 – F11, G8 – G11,
H8 – H11, J8 – J11,
K8 – K11, L8 – L11,
M8 – M11
Switching Node - connection to the output
inductor.
SGND C1 – C3, D1 –D3, E1 –E3
Signal Ground.
ENABLE F1
When set to logic level high, internal
circuitry of the device is enabled. When set
to logic level low, the PRDY pin is forced
low, the Control and Sychronous switches are
turned off, and the supply current is less than
10
µ
A.
PRDY K1
Power Ready - This pin indicates the status of
ENABLE or V
DD
. This output will be driven
low when ENABLE is logic low or when V
DD
is less than 4.4V (typ.). When ENABLE is
logic high and V
DD
is greater than 4.4V
(typ.), this output is driven high. This output
has a 10mA source and 1mA sink capability.
PWM H1
TTL-level input signal to MOSFET drivers.
NC
B4, C4, D4, E4, F2 – F4, G2 –
G4, H2 – H4, J1, J2 – J4, K3,
L1, L2, M1 – M4
This pin is not for electrical connection. It
should be attached only to dead copper.
P1-P3P4-P6P7-P9P10-P12

IP2002TRPBF

Mfr. #:
Buy IP2002TRPBF
Manufacturer:
Infineon Technologies
Description:
IC REG BUCK ADJ 30A 133BGA iPOWIR
Lifecycle:
New from this manufacturer.
Delivery:
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