LNBH21
10/20
ELECTRICAL CHARACTERISTICS FOR LNBP SERIES (T
J
= 0 to 85°C, EN=1, TTX=0/1, DSQIN=LOW,
LLC=TEN=PCL=VSEL=0, V
IN
=12V, I
O
=50mA, unless otherwise specified. See software description
section for I
2
C access to the system register).
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
IN
Supply Voltage I
O
= 750 mA TEN=VSEL=LLC=1 8 15 V
I
I
Supply Current EN=TEN=VSEL=LLC=1, NO LOAD 20 40 mA
EN=0 3.5 7
V
O
Output Voltage I
O
= 750 mA VSEL=1 LLC=0 17.3 18 18.7 V
LLC=1 18.7 19.5 20.3
V
O
Output Voltage I
O
= 750 mA VSEL=0 LLC=0 12.75 13.25 13.75 V
LLC=1 13.75 14.25 14.75
V
O
Line Regulation V
IN1
= 8 to 15V VSEL=0 5 40 mV
VSEL=1 5 60
V
O
Load Regulation VSEL=0 or 1, I
O
= 50 to 750mA 200 mV
I
MAX
Output Current Limiting ISEL = Floating or V > 3.3V 750 1000 mA
ISEL = GND 450 700
I
SC
Output Short Circuit Current VSEL=0 300 mA
VSEL=1 200
t
OFF
Dynamic Overload
protection OFF Time
PCL=0 Output Shorted 900 ms
t
ON
Dynamic Overload
protection ON Time
PCL=0 Output Shorted t
OFF
/10 ms
f
TONE
Tone Frequency TEN=1 20 22 24 KHz
A
TONE
Tone Amplitude TEN=1 0.55 0.72 0.9 V
PP
D
TONE
Tone Duty Cycle TEN=1 40 50 60 %
t
r
,t
f
Tone Rise and Fall Time TEN=1 5 8 15 µs
G
EXTM
External Modulation Gain V
OUT
/V
EXTM
, f = 10Hz to 50KHz 6
V
EXTM
External Input Voltage AC Coupling 400 mV
PP
Z
EXTM
External Modulation
Impedance
f = 10Hz to 50KHz 260
f
SW
DC/DC Converter Switching
Frequency
220 kHz
f
DETIN
Tone Detector Frequency
Capture Range
0.4Vpp sinewave 18 24 kHz
V
DETIN
Tone Detector Input
Amplitude
f
IN
=22kHz sinewave 0.2 1.5 V
PP
Z
DETIN
Tone Detector Input
Impedance
150 k
V
OL
DSQOUT Pin Logic LOW Tone present I
OL
=2mA 0.3 0.5 V
I
OZ
DSQOUT Pin Leakage
Current
Tone absent V
OH
=6V 10 µA
V
IL
DSQIN Input Pin Logic
LOW
0.8 V
V
IH
DSQIN Input Pin Logic
HIGH
2V
I
IH
DSQIN Pins Input Current V
IH
=5V 15 µA
I
OBK
Output Backward Current EN=0, V
OBK
= 18V -6 -15 mA
T
SHDN
Temperature Shutdown
Threshold
150 °C
T
SHDN
Temperature Shutdown
Hysteresis
15 °C
LNBH21
11/20
GATE AND SENSE ELECTRICAL CHARACTERISTICS (T
J
= 0 to 85°C, V
IN
= 12V)
I
2
C ELECTRICAL CHARACTERISTICS (T
J
=0to85°C,V
I
= 12V)
ADDRESS PIN CHARACTERISTICS (T
J
= 0 to 85°C, V
IN
=12V)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
R
DSON-L
Gate LOW R
DSON
I
GATE
= -100mA 4.5
R
DSON-H
Gate HIGH R
DSON
I
GATE
= 100mA 4.5
V
SENSE
Current Limit Sense Voltage 200 mV
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
IL
LOW Level Input Voltage SDA, SCL 0.8 V
V
IH
HIGH Level Input Voltage SDA, SCL 2 V
I
I
Input Current SDA, SCL, V
I
= 0.4 to 4.5V -10 10 µA
V
OL
Low Level Output Voltage SDA (open drain), I
OL
=6mA 0.6 V
f
MAX
Maximum Clock Frequency SCL 500 KHz
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
ADDR-1
"0001000" Addr Pin Voltage 0 0.7 V
V
ADDR-2
"0001001" Addr Pin Voltage 1.3 1.7 V
V
ADDR-3
"0001010" Addr Pin Voltage 2.3 2.7 V
V
ADDR-4
"0001011" Addr Pin Voltage 3.3 5 V
LNBH21
12/20
THERMAL DESIGN NOTES
During normal operation, the LNBH21 device dissipates some power. At maximum rated output current
(750mA), the voltage drop on the linear regulator lead to a total dissipated power that is typically 1.65W.
The heat generated requires a suitable heatsink to keep the junction temperature below the over
temperature protection threshold. Assuming a 45°C temperature inside the Set-Top-Box case, the total
R
thj-amb
has to be less than 48°C/W.
While this can be easily achieved using a through-hole power package that can be attached to a small
heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB
solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous
copper area of the GND layer to dissipate the heat coming from the IC body.
GivenanR
thj-case
equal to 2°C/W, a maximum of 46°C/W are left to the PCB heatsink. This figure is
achieved if a minimum of 6.5cm
2
copper area is placed just below the IC body. This area can be the inner
GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side
where the IC is placed. In figure 4, it is shown a suggested layout for the PSO-20 package with a dual
layer PCB, where the IC exposed pad connected to GND and the square dissipating area are thermally
connected through 32 vias holes, filled by solder. This arrangement, when L=25mm, achieves an R
thc-amb
of about 32°C/W.
Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground
exposed pad approximately in the middle of the dissipating area; to provide as many vias as possible; to
design a dissipating area having a shape as square as possible and not interrupted by other copper
traces.
Figure 4 : PowerSO-20 SUGGESTED PCB HEATSINK LAYOUT

TPS51640ARSLT

Mfr. #:
Manufacturer:
Texas Instruments
Description:
Switching Controllers Dual-Channel SD Controller
Lifecycle:
New from this manufacturer.
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