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IDT5V2528PGGI8

P1-P3P4-P6P7-P9
1
INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
2013 Integrated Device Technology, Inc. DSC 5971/12c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
• 1:10 fanout
• 3-level inputs for output control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Configurable 2.5V or 3.3V LVTTL outputs
•tPD Phase Error at 100MHz to 166MHz: ±150ps
• Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
• Spread spectrum compatible
• Operating Frequency:
- Std: 25MHz to 140MHz
- A: 25MHz to 167MHz
• Available in TSSOP package
• Use replacement part 87952AYI-147LF
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock loop
(PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase,
the feedback (FBOUT) output to the clock (CLK) input signal. The IDT5V2528 inputs,
IDT5V2528/A
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
19
Y1, V
DD pin 21
PLL
3
24
17
16
26
TY0, V
DDQ pin 4
13
10
20
12
Y0, V
DD pin 21
6
7
5
AV
DD
FBIN
CLK
G_Ctrl
28
22
FBOUT, V
DD pin 21
T_Ctrl
1
MODE
SELECT
TY1, VDDQ pin 25
TY2, V
DDQ pin 25
TY3, V
DDQ pin 15
TY4, V
DDQ pin 15
TY5, V
DDQ pin 11
TY6, V
DDQ pin 11
TY7, V
DDQ pin 11
PLL core, Y0, Y1, and FBOUT buffers operate from the 3.3V VDD and AVDD power
supply pins.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of the ten
outputs, up to seven may be configured for 2.5V or 3.3V LVTTL outputs. The number
of 2.5V outputs is controlled by 3-level input signals G_Ctrl and T_Ctrl, and by
connecting the appropriate VDDQ pins to 2.5V or 3.3V. The 3-level input signals may
be hard-wired to high-mid-low levels. Output signal duty cycles are adjusted to
50 percent, independent of the duty cycle at CLK. The outputs can be enabled or
disabled via the G_Ctrl input. When the G_Ctrl input is mid or high, the outputs switch
in phase and frequency with CLK; when the G_Ctrl is low, all outputs (except FB
OUT)
are disabled to the logic-low state.
Unlike many products containing PLLs, the IDT5V2528 does not require external
RC networks. The loop filter for the PLL is included on-chip, minimizing component
count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a stabilization time
to achieve phase lock of the feedback signal to the reference signal. This stabilization
time is required, following power up and application of a fixed-frequency, fixed-phase
signal at CLK, as well as following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVDD to ground.
MAY 2013
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014
2
INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
PIN CONFIGURATION
TSSOP
TOP VIEW
G_Ctrl
GND
TY1
VDDQ
TY2
GND
FBOUT
VDD
Y0
Y1
GND
TY3
VDDQ
TY6
T_Ctrl
GND
TY0
VDDQ
AVDD
CLK
FBIN
AGND
GND
TY7
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
TY4
V
DDQ
TY5
GND
18
17
11
12
16
15
13
14
Symbol Rating Max. Unit
VDD, VDDQ, AVDD Supply Voltage Range –0.5 to +4.6 V
VI
(2)
Input Voltage Range –0.5 to +5.5 V
V
O
(2)
Voltage Range applied to any –0.5 to V
output in the HIGH or LOW state VDD+0.5
IIK (VI < 0) Input Clamp Current –50 mA
IOK Output Clamp Current ±50 mA
(VO < 0 or VO > VDD)
I
O Continuous Output Current ±50 mA
(VO = 0 to VDD)
VDD or GND Continuous Current ±200 mA
TSTG Storage Temperature Range –65 to +150 ° C
TJ Junction Temperature +150 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Min. Typ. Max. Unit
VDD, AVDD
(1)
Power Supply Voltage 3 3.3 3.6 V
V
DDQ
(1)
Power Supply Voltage 2.5V Outputs 2.3 2.5 2.7 V
3.3V Outputs 3 3.3 3.6
TA Ambient Operating Temperature –40 +25 +85 ° C
RECOMMENDED OPERATING RANGE
Symbol Description Min Typ. Max. Unit
C
IN Input Capacitance — 5 — pF
VI = VDD or GND
CO Output Capacitance — 6 — pF
VI = VDD or GND
CL Load Capacitance 2.5V outputs — 20 — pF
3.3V outputs — 30 —
CAPACITANCE
(1)
NOTE:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
PIN DESCRIPTION
Terminal
Name No. Type Description
CLK
(1)
6 I Clock input
FBIN 7 I Feedback input
G_Ctrl
(2)
28 3-level 3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see
OUTPUT SELECTION table).
T_Ctrl
(2)
1 3-level 3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)
FBOUT 22 O Feedback output
TY
(7:0) 3, 10, 12, 13, O 2.5V or 3.3V Clock outputs. 1, 2, 3, 5, or 7 of these outputs may be selected as 2.5V outputs (see OUTPUT SELECTION table).
16, 17, 24, 26
Y (1:0) 19, 20 O 3.3V Clock Outputs
AVDD
(3)
5 Power 3.3V Analog power supply. AVDD provides the power reference for the analog circuitry.
AGND 8 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
VDD 21 Power 3.3V Power supply
VDDQ 4, 11, 15, 25 Power 2.5V or 3.3V Power supply for TY outputs
GND 2, 9, 14, 18 Ground Ground
23, 27
NOTES:
1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms
is required for the PLL to phase lock the feedback signal to the reference signal.
2. 3-level inputs will float to MID logic level if left unconnected.
3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
OUTPUT SELECTION
VDDQ
G_Ctrl T_Ctrl TY(7:0) Configuration
ML TY0 (2.5V) Pin 4 (2.5V)
TY1 - TY7 (3.3V) Pins 11, 15, 25 (3.3V)
MMTY1, TY2 (2.5V) Pin 25 (2.5V)
TY0, TY3 - TY7 (3.3V) Pins 4, 11, 15 (3.3V)
MHTY0 - TY2 (2.5V) Pins 4, 25 (2.5V)
TY3 - TY7 (3.3V) Pins 11, 15 (3.3V)
HLTY0 - TY4 (2.5V) Pins 4, 15, 25 (2.5V)
TY5 - TY7 (3.3V) Pin 11 (3.3V)
HMTY1 - TY7 (2.5V) Pins 11, 15, 25 (2.5V)
TY0 (3.3V) Pin 4 (3.3V)
HHTYo - TY7 (3.3V) Pins 4, 11, 15, 25 (3.3V)
STATIC FUNCTION TABLE (AVDD = 0V)
(1)
Inputs Outputs
G_Ctrl T_Ctrl CLK TY(7:0) Y(1:0) FBOUT
LXLLLL
LXH L L H
see HHHH
OUTPUT SELECTION L L L L
table running running running running
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs Outputs
G_Ctrl T_Ctrl CLK TY(7:0) Y(1:0) FBOUT
LX L L L L
LX H L L H
see OUTPUT L L L L
SELECTION table H H H H
NOTE:
1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the
control pins in a valid state.
P1-P3P4-P6P7-P9

IDT5V2528PGGI8

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Description:
IC CLK DVR ZD BUFFER PLL 28TSSOP
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