OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

83940AY-02LF

P1-P3P4-P6P7-P9P10-P12P13-P14
83940AY-02 www.icst.com/products/hiperclocks.html REV. A JULY 30, 2007
7
ICS83940-02
LOW SKEW, 1-TO-18
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0:Q17
t
PD
V
DDO
2
➤
➤
V
DD
2
LVCMOS_CLK
Q0:Q17
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAYOUTPUT RISE/FALL TIME
CLK0
nCLK0
83940AY-02 www.icst.com/products/hiperclocks.html REV. A JULY 30, 2007
8
ICS83940-02
LOW SKEW, 1-TO-18
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
83940AY-02 www.icst.com/products/hiperclocks.html REV. A JULY 30, 2007
9
ICS83940-02
LOW SKEW, 1-TO-18
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 2A,
the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
P1-P3P4-P6P7-P9P10-P12P13-P14

83940AY-02LF

Mfr. #:
Buy 83940AY-02LF
Manufacturer:
Description:
IC CLK BUFFER 2:18 200MHZ 32TQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet