MPC555 Product Brief 3
Key Features
1.2.2 U-Bus System Interface Unit (USIU)
• Clock synthesizer
• Power management
• Reset controller
• MPC555 decrementer and time base
• Real-time clock register
• Periodic interrupt timer
• Hardware bus monitor and software watchdog timer
• Interrupt controller that supports up to eight external and eight internal interrupts
• IEEE 1149.1 JTAG test access port
• External bus interface
— 24 address pins, 32 data pins
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Supports 5V inputs, provides 3.3-V outputs
1.2.3 Flexible Memory Protection Unit
• Four instruction regions and four data regions
• 4-Kbyte to 16-Mbyte region size support
• Default attributes available in one global entry
• Attribute support for speculative accesses
1.2.4 448-Kbyte Flash EEPROM Memory
• One 256-Kbyte and one 192-Kbyte module
• Page read mode
• Block (32-Kbyte) erasable
• External 4.75-V to 5.25-V program and erase power supply
1.2.5 26-Kbytes of Static RAM
• One 16-Kbyte and one 10-Kbyte module
• Fast (one-clock) access
• Keep-alive power
• Soft defect detection (SDD)
1.2.6 General-Purpose I/O Support
• Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode
• Nine general-purpose I/O pins in MIOS1 unit
• Many peripheral pins can be used for general-purpose I/O when not used for primary function
• 5-V tolerant inputs/outputs
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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