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LT4256-3IGN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LT4256-3
10
42563fa
APPLICATIO S I FOR ATIO
WUU
U
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4256-3 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The
device also provides undervoltage and overvoltage as well
as overcurrent protection while a power good output
signal indicates when the output supply voltage is ready
with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
When the power pins first make contact, transistor Q1 is
held off. If the voltage on V
CC
is between the externally
programmed undervoltage and overvoltage thresholds,
V
CC
is above 9.8V and the voltage on TIMER is less than
4.65V (typ), transistor Q1 will be turned on (Figure 6). The
voltage on GATE rises with a slope equal to 32µA/C1 and
the supply inrush current is set at:
I
INRUSH
= C
L
• 32µA/C1 (1)
where C
L
is the total load capacitance.
Figure 5. 1.6A, 48V Latchoff Application
Figure 6. Start-Up Waveforms
4256 F05
R5
0.025Ω
LT4256-3
SENSE
13
12
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
V
OUT
FB
PWRGD
RETRY
UV
OV
TIMER
GND
V
IN
48V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD
V
OUT
48V
1.6A
R4
51k
C
L
C2
33nF
C3
0.01µF
C1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
D2
SMAT70A
+
I
OUT
500mA/DIV
V
OUT
50V/DIV
5ms/DIV
4256 F06
PWRGD
50V/DIV
GATE
50V/DIV
C
L
= 125µF
LT4256-3
11
42563fa
APPLICATIO S I FOR ATIO
WUU
U
To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resis-
tor R5 reaches V
SENSETRIP
, the inrush current will be lim-
ited by the internal current limit circuitry. The voltage on
GATE is adjusted to maintain a constant voltage across the
sense resistor and TIMER begins to charge.
When the FB voltage goes above the low-to-high V
FB
threshold, PWRGD goes high.
Undervoltage and Overvoltage Detection
The LT4256-3 uses UV and OV to monitor the V
CC
voltage
to determine when it is safe to turn on the load and allow
the user the greatest flexibility for setting the operational
thresholds. UV and OV are internally connected to an
analog window comparator. Any time that UV goes below
3.6V or OV goes above 4V, GATE will be pulled low until the
UV/OV voltages return to the normal operation voltage
window (4V and 3.6V, respectively).
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of the
UV’s hysteresis will be lost, making the LT4256-3 more
susceptible to noise (V
CC
must be at least 9.8V when UV
is at its 3.6V threshold). UV is filtered with C3 to prevent
noise spikes and capacitively coupled glitches from shut-
ting down the LT4256-3 output erroneously.
To calculate UV and OV thresholds, use the following
equations:
4256 F07
R5
0.010Ω
LT4256-3
SENSE
13
10
5
7
8
16
D2
SMAT70A
15
1
2
4
9
V
CC
GATE
FB
12
V
OUT
PWRGD
RETRY
UV
OV
TIMER
GND
V
CC
48V
(SHORT PIN)
Q1
IRF540
D1
CMPZ5241BS
11V
R3
4.02k
R2
4.02k
Q2
VN2222
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
V
OUT
48V
4A
R4
51k
C
L
C2
33nF
C3
0.01µF
OFF SIGNAL
FROM MPU
C1
10nF
OPEN
UV = 36V
OV = 73V
PWRGD = 40V
GND
+
Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off
RRR
V
V
a
R
RR
V
b
kRRR k
VV
R
RR
VV
RR
R
THUVLH
THOVLH
THUVHL
THOVHL
123
4
12
3
12
4
1
2
20 1 2 3 200 3
36 1
1
23
4
36 1
12
3
=+
()
⎛
⎝
⎜
⎞
⎠
⎟
()
=
+
()
Ω≤ ++ ≤Ω
()
=+
+
⎛
⎝
⎜
⎞
⎠
⎟
()
=+
+
⎛
⎝
⎜
⎞
⎠
⎟
–
–
.;
.
where V
THULH
and V
THOVLH
are the desired UV and OV
threshold voltages when V
CC
is rising (L – H).
Figure 7 shows how the LT4256-3 is commanded to shut
off with a logic signal. This is accomplished by pulling the
gate of the open-drain MOSFET, Q2, (tied to UV) high.
LT4256-3
12
42563fa
APPLICATIO S I FOR ATIO
WUU
U
Short-Circuit Protection
The LT4256-3 features a programmable foldback current
limit with an electronic circuit breaker that protects against
short circuits or excessive load currents. The current limit
is set by placing a sense resistor (R5) between V
CC
and
SENSE. The current limit threshold is calculated as:
I
LIMIT
= 55mV/R5 (5)
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
If the LT4256-3 goes into current limit when the voltage on
FB is 0V, the current limit circuit drives GATE to force a
constant 14mV drop across the sense resistor. As the
output at FB increases, the voltage across the sense
resistor increases until FB reaches 2V, at which point the
voltage across the sense resistor is held constant at 55mV
(see Figure 8).
For a 0.025Ω sense resistor, the typical current limit is set
at 2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 106W to
27W. See the Layout Considerations section for important
information about board layout to minimize current limit
threshold error.
The LT4256-3 also features a variable overcurrent re-
sponse time. The time required for the part to regulate the
GATE voltage is a function of the voltage across the sense
resistor connected between V
CC
and SENSE. This helps to
eliminate sensitivity to current spikes and transients that
might otherwise unnecessarily trigger a current limit re-
sponse and increase MOSFET dissipation. Figure 9 shows
the response time as a function of the overdrive at SENSE.
Figure 8. Current Limit Sense Voltage vs Feedback Pin Voltage
Figure 9. Response Time to Overcurrent
14mV
0V 2V FB
4256 F08
55mV
V
CC
– V
SENSE
50 100 150 200
4256 F09
12
10
8
6
4
2
RESPONSE TIME (µs)
V
CC
– V
SENSE
(mV)
0
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LT4256-3IGN#PBF

Mfr. #:
Buy LT4256-3IGN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Controller, +48V
Lifecycle:
New from this manufacturer.
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