Table 14: DDR2 I
DD
Specifications and Conditions – 4GB (Die Revision C) (Continued)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
Parameter Symbol -1GA
-80E/
-800 -667 Units
Operating bank interleave read current: All device banks interleaving
reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK
(I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
I
DD7
1
2178 2088 1908 mA
Notes:
1. Value calculated as one module rank in this operating condition; all other module ranks
in I
DD2P
(CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 15: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
1.7 3.6 V
Input high voltage: logic 1; All inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: logic 0; All inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
– 0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 16: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F – 300 ns 2
SDA and SCL rise time
t
R – 300 ns 2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I – 50 ns
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 UDIMM
Serial Presence-Detect
PDF: 09005aef83c6d17f
htf18c128_256_512x72az.fm - Rev. E 4/14 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
