www.austriamicrosystems.com/Supervisors/AS1910 Revision 1.03 8 - 16
AS1910 - AS1915
Datasheet - Detailed Description
8 Detailed Description
The AS1910 - AS1915 supervisory circuits were designed to generate a reset when one of the two monitored supply voltages falls below its
factory-trimmed trip threshold (see VTH on page 4 and VTH2 on page 4), and to maintain the reset for a minimum timeout period (see tRP on
page 5) after all supplies have stabilized.
The integrated watchdog timer (see Watchdog Input on page 10) helps mitigate against bad programming code or clock signals, and/or poor
peripheral response. An active-low manual reset input (see Manual Reset Input on page 10) allows for an externally activated system reset.
8.1 RESET/RESETN
Whenever one of the monitored voltages falls below its reset threshold, the RESET output (AS1910, AS1912, AS1913, AS1915) asserts low or
the RESETN output (AS1911, AS1914) asserts high. Once all monitored voltages have stabilized, an internal timer keeps the reset asserted for
the reset timeout period (t
RP). After the tRP period, the RESET or RESETN output return to their original state (see Figure 10).
Figure 9. Functional Diagram of V
CC Supervisory Application
Figure 10. Reset Timing Diagram
AS1913/AS1914/AS1915
Reset Timeout Delay
Generator
Watchdog Transition
Detector
Watchdog
Timer
+
–
1.26V
VCC
0.63V
1.26V
5
VCC2
2
GND
6
VCC
4
WDI
1
RESETN/
RESET
3
MRN
1V
t
RD
tRP
tRP
tRD
VTHVTH
VCC
RESETN
RESET
GND
1V