9DBL0841BKILF Datasheet 9DBL0841BKILF, 9DBL0851BKILF | P13-P15

FEBRUARY 9, 2017 13 8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

9DBL0841 / 9DBL0851 DATASHEET

SMBus Table: Impedance Control

Byte 11 Name Control Function Type 0 1 Default

Bit 7

FB_imp[1] RW 00=33



DIF Zout 10=100



DIF Zout

Bit 6

FB_imp[0] RW 01=85



DIF Zout 11 = Reserved

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

STP[1] RW 00 = Low/Low 10 = High/Low 0

Bit 0

STP[0] RW 01 = HiZ/HiZ 11 = Low/High 0

Note: xx41 = 10, xx51 = 01, P1 = factory programmable.

SMBus Table: Impedance Control

Byte 12 Name Control Function Type 0 1 Default

Bit 7

DIF3_imp[1] DIF3 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 6

DIF3_imp[0] DIF3 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 5

DIF2_imp[1] DIF2 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 4

DIF2_imp[0] DIF2 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 3

DIF1_imp[1] DIF1 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 2

DIF1_imp[0] DIF1 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 1

DIF0_imp[1] DIF0 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 0

DIF0_imp[0] DIF0 Zout RW 01=85



DIF Zout 11 = Reserved

Note: xx41 = 10, xx51 = 01, P1 = factory programmable.

SMBus Table: Impedance Control

Byte 13 Name Control Function Type 0 1 Default

Bit 7

DIF7_imp[1] DIF7 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 6

DIF7_imp[0] DIF7 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 5

DIF6_imp[1] DIF6 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 4

DIF6_imp[0] DIF6 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 3

DIF5_imp[1] DIF5 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 2

DIF5_imp[0] DIF5 Zout RW 01=85



DIF Zout 11 = Reserved

Bit 1

DIF4_imp[1] DIF4 Zout RW 00=33



DIF Zout 10=100



DIF Zout

Bit 0

DIF4_imp[0] DIF4 Zout RW 01=85



DIF Zout 11 = Reserved

Note: xx41 = 10, xx51 = 01, P1 = factory programmable.

SMBus Table: Pull-up Pull-down Control

Byte 14 Name Control Function Type 0 1 Default

Bit 7

OE3_pu/pd[1] RW 00=None 10=Pup 0

Bit 6

OE3_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 5

OE2_pu/pd[1] RW 00=None 10=Pup 0

Bit 4

OE2_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 3

OE1_pu/pd[1] RW 00=None 10=Pup 0

Bit 2

OE1_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 1

OE0_pu/pd[1] RW 00=None 10=Pup 0

Bit 0

OE0_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Note: These values are for xx41 and xx51. P1 is factory programmable.

Feedback Zout

Reserved

True/Complement DIF Output

Disable State

see Note

OE3 Pull-up(PuP)/

Pull-down(Pdwn) control

OE2 Pull-up(PuP)/

Pull-down(Pdwn) control

OE1 Pull-up(PuP)/

Pull-down(Pdwn) control

OE0 Pull-up(PuP)/

Pull-down(Pdwn) control

see Note

8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 14 FEBRUARY 9, 2017

9DBL0841 / 9DBL0851 DATASHEET

Byte 15 Name Control Function Type 0 1 Default

Bit 7

OE7_pu/pd[1] RW 00=None 10=Pup 0

Bit 6

OE7_pu/pd0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 5

OE6_pu/pd[1] RW 00=None 10=Pup 0

Bit 4

OE6_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 3

OE5_pu/pd[1] RW 00=None 10=Pup 0

Bit 2

OE5_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Bit 1

OE4_pu/pd[1] RW 00=None 10=Pup 0

Bit 0

OE4_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1

Note: These values are for xx41 and xx51. P1 is factory programmable.

SMBus Table: Pull-up Pull-down Control

Byte 16 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

CKPWRGD_PD_pu/pd[1] RW 00=None 10=Pup 1

Bit 0

CKPWRGD_PD_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 0

Note: These values are for xx41 and xx51. P1 is factory programmable.

Bytes 17 is Reserved and and reads back 0h00.

SMBus Table: Polarity Control

Byte 18 Name Control Function Type 0 1 Default

Bit 7

OE7_polarity Sets OE7 polarity RW Enabled when Low Enabled when High 0

Bit 6

OE6_polarity Sets OE6 polarity RW Enabled when Low Enabled when High 0

Bit 5

OE5_polarity Sets OE5 polarity RW Enabled when Low Enabled when High 0

Bit 4

OE4_polarity Sets OE4 polarity RW Enabled when Low Enabled when High 0

Bit 3

OE3_polarity Sets OE3 polarity RW Enabled when Low Enabled when High 0

Bit 2

OE2_polarity Sets OE2 polarity RW Enabled when Low Enabled when High 0

Bit 1

OE1_polarity Sets OE1 polarity RW Enabled when Low Enabled when High 0

Bit 0

OE0_polarity Sets OE0 polarity RW Enabled when Low Enabled when High 0

SMBus Table: Polarity Control

Byte 19 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CKPWRGD_PD

Determines

CKPWRGD_PD polarity

Power Down when

Low

Power Down when

High

Reserved

OE6 Pull-up(PuP)/

Pull-down(Pdwn) control

OE5 Pull-up(PuP)/

Pull-down(Pdwn) control

OE4 Pull-up(PuP)/

Pull-down(Pdwn) control

Reserved

CKPWRGD_PD Pull-up(PuP)/

Pull-down(Pdwn) control

OE7 Pull-up(PuP)/

Pull-down(Pdwn) control

FEBRUARY 9, 2017 15 8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

9DBL0841 / 9DBL0851 DATASHEET

Marking Diagrams

Notes:

1. “LOT” is the lot sequence number.

2. “COO” denotes country of origin.

3. YYWW is the last two digits of the year and week that the part was assembled.

4. Line 2: truncated part number

5. “L” denotes RoHS compliant package.

6. “I” denotes industrial temperature range device.

Thermal Characteristics

ICS

DBL0841BI

YYWW

COO

LOT

ICS

DBL0851BI

YYWW

COO

LOT

ICS

B8P1000I

YYWW

COO

LOT

PARAMETER SYMBOL CONDITIONS PKG

TYP

VALUE

UNITS NOTES

Junction to Case 33 °

C/W

Junction to Base 2.1 °

C/W

JA0

Junction to Air, still air 37 °

C/W

JA1

Junction to Air, 1 m/s air flow 30 °

C/W

JA3

Junction to Air, 3 m/s air flow 27 °

C/W

JA5

Junction to Air, 5 m/s air flow 26 °

C/W

ePad soldered to board

Thermal Resistance NDG48

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

9DBL0841BKILF

Mfr. #:

Buy 9DBL0841BKILF

Manufacturer:

IDT

Description:

Clock Buffer 8 O/P 3.3V PCIE ZERO DELAY BUF

Lifecycle:

New from this manufacturer.

Delivery:

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9DBL0841BKILF

9DBL0841BKILF

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