AD8345
Rev. B | Page 3 of 20
SPECIFICATIONS
V
S
= 5 V; LO = −2 dBm @ 800 MHz; 50 Ω source and load impedances; I and Q inputs 0.7 V ±0.3 V on each side for a 1.2 V p-p
differential input, I and Q inputs driven in quadrature @ 1 MHz baseband frequency. T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF OUTPUT
Operating Frequency
1
140 1000 MHz
Output Power 0.5 dBm 140 MHz
0.5 dBm 220 MHz
−3 −1 +2 dBm 800 MHz
Output P1dB 2.5 dBm
Noise Floor −155 dBm/Hz 20 MHz offset from LO, all BB inputs at 0.7 V
Quadrature Error 0.5 Degree rms CDMA IS95 setup (see Figure 38)
I/Q Amplitude Balance 0.2 dB CDMA IS95 setup (see Figure 38)
LO Leakage −41 dBm 140 MHz
−40 dBm 220 MHz
−42 −33 dBm 800 MHz
Sideband Rejection −33 dBc 140 MHz
−48 −40 dBc 220 MHz
−42 −34 dBc 800 MHz
Third Order Distortion −52 dBc
Second Order Distortion −60 dBc
Equivalent Output IP3 25 dBm
Equivalent Output IP2 59 dBm
Output Return Loss (S22) −20 dB
RESPONSE TO CDMA IS95 See Figure 38
BASEBAND SIGNALS
ACPR −72 dBc
EVM 1.3 %
Rho 0.9995
LO INPUT
LO Drive level −10 −2 0 dBm
LOIP Input Return Loss (S11)
2
−5 dB No termination on LOIP, LOIN at ac ground
−9 dB 50 Ω terminating resistor, differential drive via balun
BASEBAND INPUTS
Input Bias Current 10 μA
Input Capacitance 2 pF
DC Common Level 0.6 0.7 0.8 V
Bandwidth (3 dB) 80 MHz Full power (0.7 V ±0.3 V on each input, see Figure 4)
ENABLE
Turn-On 2.5 μs Enable high to output within 0.5 dB of final value
Turn-Off 1.5 μs Enable low to supply current dropping below 2 mA
ENBL High Threshold (Logic 1) +V
S
/2 V
ENBL Low Threshold (Logic 0) +V
S
/2 V
POWER SUPPLIES
Voltage 2.7 5.5 V
Current Active 50 65 78 mA
Current Standby 70 μA
1
For information on operation below 140 MHz, see Figure 29.
2
See the LO Interface section for more details on input matching.
