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AD7538JR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD7538
Rev. B | Page 12 of 16
PROGRAMMABLE GAIN AMPLIFIER
The circuit shown in Figure 9 provides a programmable gain
amplifier (PGA). In it the DAC behaves as a programmable
resistance and thus allows the circuit gain to be digitally
controlled.
AD7538
N
I
OUT
V
DD
V
DD
V
SS
V
OUT
V
IN
V
REF
GND
DIGITAL
INPUT
A
A
R
FB
NOTES
1. RESISTOR R
FB
IS ACTUALLY
INCLUDED ON THE DICE.
01139-009
Figure 9. Programmable Gain Amplifier (PGA)
The transfer function of Figure 9 is:
FB
EQ
IN
OUT
R
R
V
V
Gain −==
(1)
R
EQ
is the equivalent transfer impedance of the DAC from the
V
REF
pin to the I
OUT
pin and can be expressed as
N
R
R
IN
n
EQ
2
= (2)
where:
n is the resolution of the DAC.
N is the DAC input code in decimal.
R
IN
is the constant input impedance of the DAC (R
IN
= R
LAD
).
Substituting this expression into Equation 1 and assuming
zero gain error for the DAC (R
IN
= R
FB
), the transfer function
simplifies to
NV
V
n
IN
OUT
2
−=
(3)
The ratio N/2
n
is commonly represented by the term, D, and, as
such, is the fractional representation of the digital input word.
DNV
V
n
IN
OUT
12 −
=
−
−= (4)
Equation 4 indicates that the gain of the circuit can be varied
from 16,384 down to unity (actually 16,384/16,383) in 16,383
steps. The all 0s code is never applied. This avoids an open-loop
condition thereby saturating the amplifier. With the all 0s code
excluded there remains (2
n
– 1) possible input codes allowing a
choice of (2
n
– 1) output levels. In decibels the dynamic range is
)
dB8412log20log20
1010
=−=
n
IN
OUT
V
V
AD7538
Rev. B | Page 13 of 16
APPLICATION HINTS
OUTPUT OFFSET
CMOS DACs in circuits such as Figure 6 and Figure 8 exhibit
a code dependent output resistance, which in turn can cause a
code dependent error voltage at the output of the amplifier.
The maximum amplitude of this error, which adds to the DAC
nonlinearity, depends on V
OS
, where V
OS
is the amplifier input
offset voltage. To maintain specified accuracy with V
REF
at 10 V,
it is recommended that V
OS
be no greater than 0.25 mV, or (25 ×
10
−6
) (V
REF
), over the temperature range of operation. The AD711 is
a suitable op amp. The op amp has a wide bandwidth and high
slew rate and is recommended for ac and other applications
requiring fast settling.
GENERAL GROUND MANAGEMENT
Because the AD7538 is specified for high accuracy, it is impor-
tant to use a proper grounding technique. AC or transient
voltages between AGND and DGND can cause noise injection
into the analog output. The simplest method of ensuring that
voltages at AGND and DGND are equal is to tie AGND and
DGND together at the AD7538. In more complex systems
where the AGND and DGND intertie on the backplane, it is
recommended that two diodes be connected in inverse
parallel between the AD7538 AGND and DGND pins
(1N914 or equivalent).
MICROPROCESSOR INTERFACING
The AD7538 is designed for easy interfacing to 16-bit micro-
processors and can be treated as a memory mapped peripheral.
This reduces the amount of external logic needed for interfacing
to a minimal.
AD7538-TO-8086 INTERFACE
Figure 10 shows the 8086 processor interface to a single device.
In this setup, the double buffering feature (using
LDAC
) of the
DAC is not used. The 14-bit word is written to the DAC in one
MOVE instruction and the analog output responds
immediately.
ADDRESS BUS
DATA BUSAD0 TO AD15
WR
ALE
AD13
AD0
CS
LDAC
WR
DB0 TO DB13
8096
AD7538
1
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
01139-010
16-BIT
LATCH
ADDRESS
DECODE
Figure 10. AD7538-to-8086 Interface Circuit
In a multiple DAC system, the double buffering of the AD7538
allows the user to simultaneously update all DACs. In Figure 11,
a 14-bit word is loaded to the input registers of each of the DACs
in sequence. Then, with one instruction to the appropriate
address, CS4 (that is,
LDAC
) is brought low, updating all the
DACs simultaneously.
ADDRESS BUS
DATA BUSAD0 TO AD15
WR
ALE CS
LDAC
WR
DB0 TO DB13
8096
AD7538
1
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
01139-011
16-BIT
LATCH
ADDRESS
DECODE
CS4
CS3 CS2
CS1
CS
LDAC
WR
DB0 TO DB13
AD7538
1
CS
LDAC
WR
DB0 TO DB13
AD7538
1
Figure 11. AD7538-to-8086 Interface: Multiple DAC System
AD7538-TO-MC68000 INTERFACE
Figure 12 shows the MC68000 processor interface to a single
device. In this setup, the double buffering feature of the DAC
is not used and the appropriate data is written into the DAC in
one MOVE instruction.
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
D0 TO D15
A1 TO A23
R/W
DTACK
AS
CS
LDAC
WR
DB0 TO DB13
MC68000
AD7538
1
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
01139-012
Figure 12. AD7538-to-MC68000 Interface
AD7538
Rev. B | Page 14 of 16
DIGITAL FEEDTHROUGH
The digital inputs to the AD7538 are directly connected to the
microprocessor bus in the preceding interface configurations.
These inputs are constantly changing even when the device is
not selected. The high frequency logic activity on the bus can
feed through the DAC package capacitance to show up as noise
on the analog output. To minimize this digital feedthrough
isolate the DAC from the noise source. Figure 13 shows an
interface circuit, which uses this technique. All data inputs are
latched from the bus by the
CS
signal. One may also use other
means, such as peripheral interface devices, to reduce the digital
feedthrough.
D0 TO D15
WR
A0 TO A15
CS
LDAC
WR
DB0 TO DB13
MICRO-
PROCESSOR
SYSTEM
AD7538
1
1
LINEAR CIRCUITRY OMITTED FOR CLARITY.
01139-013
ADDRESS
DECODE
16-BIT
LATCH
EN
Figure 13. AD7538 Interface Circuit Using Latches to Minimize Digital
Feedthrough
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7538JR

Mfr. #:
Buy AD7538JR
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC LC2MOS 14-bit uP-compatible
Lifecycle:
New from this manufacturer.
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