AD7538
Rev. B | Page 10 of 16
CIRCUIT INFORMATION
EQUIVALENT CIRCUIT ANALYSIS
Figure 5 shows an equivalent circuit for the analog section
of the AD7538 DAC. The current source I
LEAKAGE
is composed
of surface and junction leakages. The R
O
resistor denotes the
equivalent output resistance of the DAC, which varies with
input code. C
OUT
is the capacitance due to the current steering
switches and varies from about 90 pF to 180 pF (typical values)
depending upon the digital input. g(V
REF
, N) is the Thevenin
equivalent voltage generator due to the reference input voltage,
V
REF
, and the transfer function of the DAC ladder, N.
I
LEAKAGE
C
OUT
I
OUT
AGND
R
FB
R
O
R/4
g (V
REF
, N)
01139-005
Figure 5. AD7538 Equivalent Analog Output Circuit
DIGITAL SECTION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close as possible to 0 V and 5 V logic levels.
UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
Figure 6 shows the circuit diagram for unipolar binary
operation. With an ac input, the circuit performs 2-quadrant
multiplication. The code table for Figure 6 is given in Table 6.
Capacitor C1 provides phase compensation and helps prevent
overshoot and ringing when high-speed op amps are used.
619
5 24
231
20
21
22
2
3
4
DB13 TO DB0 DGND
V
DD
V
REF
V
IN
R
FB
I
OUT
DD
V
O
–15V
AGND
V
SS
LDAC
CS
WR
LDAC
CS
WR
AD7538
A1
R3
1kΩ
R2
10Ω
R1
20Ω
R4
47kΩ
INPUT DATA
DIGITAL
GND
C2
4.7µF
C1
33pF
ANALOG
GND
AD711
01139-006
+
Figure 6. Unipolar Binary Operation
Table 6. Unipolar Binary Code Table
Binary Number In
DAC Register
Analog Output, V
OUT
MSB LSB
11 1111 1111 1111 −V
IN
(16,383/16,384)
10 0000 0000 0000 −V
IN
(8192/16,384) = −½V
IN
00 0000 0000 0001 −V
IN
(1/16,384)
00 0000 0000 0000 0 V
For zero offset adjustment, the DAC register is loaded with
all 0s and amplifier offset (V
OS
) adjusted so that V
OUT
is 0 V.
Adjusting V
OUT
to 0 V is not necessary in many applications,
but it is recommended that V
OS
be no greater than (25 × 10
−6
)
(V
REF
) to maintain specified DAC accuracy (see the Application
Hints section).
Full-scale trimming is accomplished by loading the DAC
register with all 1s and adjusting R1 so that V
OUTA
= −V
IN
(16,383/16,384). For high temperature operation, resistors
and potentiometers should have a low temperature coefficient.
In many applications, because of the excellent gain TC and
gain error specifications of the AD7538, gain error trimming is
not necessary. In fixed reference applications, full scale can also
be adjusted by omitting R1 and R2 and trimming the reference
voltage magnitude.
