ADuM1510 Data Sheet
Rev. D | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD1
Supply Voltage for Isolator Side 1 (4.5 V to 5.5 V).
2, 8 GND
1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to
GND
1
is recommended.
3 V
IA
Logic Input A.
4 V
IB
Logic Input B.
5 V
IC
Logic Input C.
6 V
ID
Logic Input D.
7 V
IE
Logic Input E.
9, 15 GND
2
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to
GND
2
is recommended.
10 V
OE
Logic Output E.
11 V
OD
Logic Output D.
12 V
OC
Logic Output C.
13 V
OB
Logic Output B.
14 V
OA
Logic Output A.
16 V
DD2
Supply Voltage for Isolator Side 2 (4.5 V to 5.5 V).
Table 8. Truth Table (Positive Logic)
V
Ix
Input
1
V
DD1
State
V
DD2
State
V
Ox
Output
1
Description
H Powered Powered H Normal operation, data is high.
L Powered Powered L Normal operation, data is low.
X Unpowered Powered L
Input unpowered. Outputs return to input state within 1 µs of V
DD1
power restoration.
See the Power-Up/Power-Down Considerations section for more details.
X Powered Unpowered Z
Output unpowered. Output pins are in high impedance state. Outputs return to
input state within 1 µs of V
DD2
power restoration. See the Power-Up/Power-Down
Considerations section for more details.
1
V
Ix
and V
Ox
refer to the input and output signals of a given channel (A, B, C, D, or E).
V
DD1
1
GND
1
*
2
V
IA
3
V
IB
4
V
DD2
16
GND
2
*
15
V
OA
14
V
OB
13
V
IC
5
V
OC
12
V
ID
6
V
OD
11
V
IE
7
V
OE
10
GND
1
*
8
GND
2
*
9
ADuM1510
TOP VIEW
(Not to Scale)
*
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND
1
IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND
2
IS RECOMMENDED.
0
6790-002
Data Sheet ADuM1510
Rev. D | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Figure 4. Typical Input Supply Current per Channel vs. Data Rate
Figure 5. Typical Output Supply Current per Channel vs. Data Rate
(No Output Load)
Figure 6. Typical Output Supply Current per Channel vs. Data Rate
(15 pF Output Load)
Figure 7. Typical Total V
DD1
Supply Current vs. Data Rate
Figure 8. Typical Total V
DD2
Supply Current vs. Data Rate
(15 pF Output Load)
CASE TEMPERATURE (°C)
SAFETY-LIMITING CURRENT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE 1
SIDE 2
06790-003
DATA RATE (Mbps)
V
DD1
CURRENT/CHANNE L (mA)
0
0
1.6
1.2
1.4
1.0
0.8
0.6
0.4
0.2
2
4 6 8 10
06790-004
DATA RATE (Mbps)
V
DD2
CURRENT/CHANNE L (mA)
0
0
1.6
1.2
1.4
1.0
0.8
0.6
0.4
0.2
2 4 6 8 10
06790-005
DATA RATE (Mbps)
V
DD2
CURRENT/CHANNEL, 15pF LOAD (mA)
0
0
1.6
1.2
1.4
1.0
0.8
0.6
0.4
0.2
2 4 6 8 10
06790-006
DAT
A RA
TE (Mbps)
V
DD1
CURRENT (mA)
0
0
8
6
7
5
4
3
2
1
2 4 6
8 10
06790-007
DATA RATE (Mbps)
V
DD2
CURRENT, 15pF LOAD (mA)
0
0
8
6
7
5
4
3
2
1
2 4 6 8 10
06790-008
ADuM1510 Data Sheet
Rev. D | Page 8 of 12
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM1510 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 9). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V
DD1
and between Pin 15 and Pin 16
for V
DD2
. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin must not exceed 10 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should
also be considered unless the ground pair on each package side
is connected close to the package.
Figure 9. Recommended PCB Layout
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to a logic high output.
Figure 10. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM1510 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs among multiple ADuM1510
components operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output.
If the decoder receives no pulses for more than approximately 5 μs,
the input side is assumed to be unpowered or nonfunctional, in
which case, the isolator output is forced to a default low state by
the watchdog timer circuit (see Table 8).
The limitation on the magnetic field immunity of the device is
set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The analysis below defines such conditions. In the follow-
ing analysis, the ADuM1510 is examined in a 3 V operating
condition because it represents the most susceptible mode of
operation of all products in its product family.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold of approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) Σπr
n
2
; n = 1, 2, … N
where:
β is the magnetic flux density (gauss).
r
n
is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1510 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field can be calculated, as shown in Figure 11.
Figure 11. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approximately
50% of the sensing threshold and does not cause a faulty output
transition. Similarly, if such an event occurs during a transmitted
pulse (and is of the worst-case polarity), the received pulse is
reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
V
IE
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
V
OE
GND
2
ADuM1510
0
6790-009
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
06790-010
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06790-011

ADUM1510BRWZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators 5-CH Unidirectional Digital
Lifecycle:
New from this manufacturer.
Delivery:
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