MAX7031
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
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Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega-
tive input of the data-slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
3 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Peak Detectors
The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 4, create DC output voltages equal to
the high- and low-peak values of the filtered demodulat-
ed signal. The resistors provide a path for the capaci-
tors to discharge, allowing the peak detectors to
dynamically follow peak changes of the data filter out-
put voltages.
The maximum and minimum peak detectors can be
used together to form a data slicer threshold voltage at
a value midway between the maximum and minimum
voltage levels of the data stream (see the
Data Slicer
section and Figure 4). Set the RC time constant of the
peak-detector combining network to at least 5 times the
data period.
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX7031 peak detec-
tors correct these problems by temporarily tracking the
incoming baseband filter voltage when an AGC state
switch occurs, or by forcing the peak detectors to track
the baseband filter output voltage until all internal cir-
cuits are stable following an enable pin low-to-high
transition. The peak detectors exhibit a fast attack/slow
decay response. This feature allows for an extremely
fast startup or AGC recovery.
Transmitter
Power Amplifier (PA)
The PA of the MAX7031 is a high-efficiency, open-
drain, switch-mode amplifier. The PA with proper out-
put- matching network can drive a wide range of
antenna impedances, which includes a small-loop PCB
trace and a 50Ω antenna. The output-matching network
for a 50Ω antenna is shown in the
Typical Application
Circuit
. The output-matching network suppresses the
carrier harmonics and transforms the antenna imped-
ance to an optimal impedance at PAOUT (pin 5). The
optimal impedance at PAOUT is 250Ω.
When the output-matching network is properly tuned,
the PA transmits power with a high overall efficiency of
up to 32%. The efficiency of the PA itself is more than
46%. The output power is set by an external resistor at
PAOUT, and is also dependent on the external antenna
and antenna-matching network at the PA output.
Envelope Shaping
The MAX7031 features an internal envelope-shaping
resistor, which connects between the open-drain output
of the PA and the power supply. The envelope-shaping
resistor slows the turn-on/turn-off of the PA. Envelope
shaping is not necessary for FSK. For most applica-
tions, the PA pullup inductor should be connected to
PAVDD instead of ROUT.
Fractional-N Phase-Locked Loop (PLL)
The MAX7031 utilizes a fully integrated, fractional-N
PLL for its transmit frequency synthesizer. All PLL com-
ponents, including the loop filter, are integrated inter-
nally. The loop bandwidth is approximately 200kHz.
Power-Supply Connections
The MAX7031 can be powered from a 2.1V to 3.6V sup-
ply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is
used, then the on-chip linear regulator reduces the 5V
supply to the 3V needed to operate the chip.
To operate the MAX7031 from a 3V supply, connect
PAVDD, AVDD, DVDD, and HVIN to the 3V supply.
When using a 5V supply, connect the supply to HVIN
only and connect AVDD, PAVDD, and DVDD together.
In both cases, bypass PAVDD, DVDD, and HVIN to
GND with a 0.01µF and 220pF capacitor and bypass
AVDD to GND with a 0.1µF and 220pF capacitor.
