IRLMS6702TRPBF

IRLMS6702PbF
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
100
200
300
400
1 10 100
C, Capacitance (pF)
A
DS
-V , Drain-to-Source Voltage (V)
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
2
4
6
8
10
0246810
G
GS
A
-V , Gate-to-Source Voltage (V)
Q , Total Gate Charge (nC)
I = -1.6A
V = -16V
FOR TEST CIRCUIT
SEE FIGURE 9
D
DS
0.1
1
10
100
0.4 0.6 0.8 1.0 1.2 1.
4
T = 25°C
T = 150°C
J
J
V = 0V
GS
SD
SD
A
-I , Reverse Drain Current (A)
-V , Source-to-Drain Voltage (V)
0.1
1
10
100
1 10 100
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T = 25°C
T = 150°C
Single Pulse
A
-I , Drain Current (A)
-V , Drain-to-Source Voltage (V)
DS
D
A
J
100µs
1ms
10ms
IRLMS6702PbF
www.irf.com 5
Fig 10b. Switching Time Waveforms
Fig 10a. Switching Time Test Circuit
Fig 9a. Basic Gate Charge Waveform
Fig 9b. Gate Charge Test Circuit
V
DS
-4.5V
Pulse Width ≤ 1 µs
Duty Factor 0.1 %
R
D
V
GS
V
DD
R
G
D.U.T.
+
-
Q
G
Q
GS
Q
GD
V
G
Charge
-4.5V
V
DS
9
0%
1
0%
V
GS
t
d(on)
t
r
t
d(off)
t
f
D.U.T.
V
D
S
I
D
I
G
-3mA
V
GS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
0.1
1
10
100
0.00001 0.0001 0.001 0.01 0.1 1 10 100
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
J DM thJA A
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJA
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRLMS6702PbF
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Peak Diode Recovery dv/dt Test Circuit
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
*
V
GS
*
**
[ ]
[ ]
*** V
GS
= 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 12. For P-channel HEXFET
®
power MOSFETs

IRLMS6702TRPBF

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
MOSFET MOSFT P-Ch -2.3A 200mOhm 5.8nC LogLvl
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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