ADRF5045 Data Sheet
Rev. 0 | Page 10 of 14
THEORY OF OPERATION
The ADRF5045 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The ADRF5045 incorporates a driver to perform logic functions
internally and to provide the user with the advantage of a simplified
control interface. The driver features two digital control input
pins (V1 and V2) that control the state of the RF paths.
Depending on the logic level applied to the V1 and V2 pins, one
RF path is in an insertion loss state, while the other three paths
are in an isolation state (see Table 5). The insertion loss path
conducts the RF signal equally well in both directions between
the RF throw port and the RF common port, and the isolation
paths provides high loss between the RF throw ports terminated
to internal 50 Ω resistors and the insertion loss path.
The ideal power-up sequence for the ADRF5045 is as follows:
1. Power up GND.
2. Power up VDD and VSS. The relative order is not
important.
3. Power up the digital control inputs. The relative order of
the logic control inputs is not important. However,
powering the digital control inputs before the VDD supply
can inadvertently forward bias and damage the internal
ESD protection structures.
4. Apply an RF input signal. The design is bidirectional; the
RF input signal can be applied to the RFC port while the
RF throw ports are outputs or vice versa. The RF ports are
dc-coupled to 0 V, and no dc blocking is required at the RF
ports when the RF line potential is equal to 0 V.
Table 5. Control Voltage Truth Table
Digital Control Input RF Paths
V1 V2 RF1 to RFC RF2 to RFC RF3 to RFC RF4 to RFC
Low Low Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off )
High Low Isolation (off) Insertion loss (on) Isolation (off) Isolation (off)
Low High Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off)
High High Isolation (off) Isolation (off) Isolation (off) Insertion loss (on)
Data Sheet ADRF5045
Rev. 0 | Page 11 of 14
APPLICATIONS INFORMATION
EVALUATION BOARD
Figure 22 shows the top view of the ADRF5045-EVA L Z , and
Figure 23 shows the cross sectional view of the ADRF5045-
EVA L Z .
16314-023
Figure 22. Evaluation Board Layout, Top View
RO4003
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5oz Cu (0.7mil)
0.5 oz Cu (0.7mil)
W = 14mil
G = 5mil
T = 0.7mil
H = 8mil
TOTAL THICKNESS ≈ 62mil
16314-022
Figure 23. Evaluation Board (Cross Sectional View)
The ADRF5045-EVA L Z is a 4-layer evaluation board. Each
copper layer is 0.7 mil (0.5 oz) and separated by dielectric
materials. All RF and dc traces are routed on the top copper
layer, and the inner and bottom layers are grounded planes that
provide a solid ground for the RF transmission lines. The top
dielectric material is 8 mil Rogers RO4003, offering optimal
high frequency performance. The middle and bottom dielectric
materials provide mechanical strength. The overall board
thickness is 62 mil, which allows 2.4 mm RF launchers to be
connected at the board edges.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and a
ground clearance of 5 mil, to have a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, as many plated
through vias as possible are arranged around transmission lines
and under the exposed pad of the package.
Figure 24 shows the actual ADRF5045-EVA L Z with component
placement. Two power supply ports are connected to the VDD
and VSS test points (TP1 and TP4), control voltages are connected
to the V1 and V2 test points (TP2 and TP3), and the ground
reference is connected to the GND test point (TP5).
16314-024
Figure 24. Evaluation Board Component Placement
On the control traces (V1 and V2), a 0 resistor connects the
test points to the pins on the ADRF5045. On the supply traces
(VDD and VSS), a 100 pF bypass capacitor filters high frequency
noise. Additionally, unpopulated components positions are
available for applying extra bypass capacitors.
The RF input and output ports (RFC, RF1, RF2, RF3, and RF4)
are connected through 50 Ω transmission lines to the 2.4 mm
RF launchers (J1 to J5). These high frequency RF launchers are
by contact and not soldered onto the board. A thru calibration
line connects the unpopulated J6 and J7 launchers; this
transmission line is used to estimate the loss of the PCB
over the environmental conditions being evaluated.
The schematic of the ADRF5045-EVA L Z is shown in Figure 25.
ADRF5045 Data Sheet
Rev. 0 | Page 12 of 14
RF2
GND
GND
RF1
GND
PAD
GND
RF4
GND
GND
GND
RF3
GND
GND
GND
1
1
RF2
RF1
J1
J2
RFC
GND
GND
AGND
AGND
R1
R2
VDD
VSS
V1
V2
AGND
TP1
TP5
TP2
TP3
TP4
GND
V2
V1
VDD
GND
VSS
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C1
100pF
C7
0.1µF
DNI
AGND
C8
0.1µF
DNI
AGND
C5
10µF
DNI
AGND
C4
0.1µF
DNI
AGND
U1
ADRF5045
19
20
21
22
23
24
PAD
AGND AGND
AGND
C2
100pF
C3
0.1µF
DNI
C6
10µF
DNI
1 1 1 1 1
AGND
2 3 4 5
AGND
2 3 4 5
1
RFC
J3
AGND
2 3 4 5
1
RF4
J4
AGND
2 3 4 5
1
RF3
J5
AGND
2 3 4 5
1
THRU_CAL
DNI DNI
J6
AGND
2 3 4
5
1
J7
AGND
25 4 3
16314-025
Figure 25. ADRF5045-EVALZ Evaluation Board Schematic
Table 6. Evaluation Board Components
Component Default Value Description
C1, C2
100 pF
Capacitors, C0402 package
C5, C6 10 µF Capacitors, C3216 package, do not install (DNI)
C3, C4, C7, C8 0.1 µF Capacitors, C0402 package, DNI
J1 to J7 Not applicable 2.4 mm end launch connector (Southwest Microwave: 1492-04A-5)
R1, R2 0 Ω Resistors, 0402 package
TP1 to TP5 Not applicable Through-hole mount test point
U1 ADRF5045 ADRF5045 digital attenuator, Analog Devices, Inc.
PCB 08-042615-01 Evaluation PCB, Analog Devices

ADRF5045BCCZN-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs Low insertion loss SP4T,30GHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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