Ver.2017-12-07
FUNCTIONAL DESCRIPTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Normally, the CLR terminal should be "H" level.
(2) Data Transmission
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
the clock signal should be controlled for data order.
(3) Cascade Connection
The serial data input from DATA terminal is output from the SO terminal through internal shift register
unrelated with the CLR and STB status.
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
to protect the noise.
CLK
STB CLR
OPERATION
X X L
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
H H
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
L
L H
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
H
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
Note 1) X: Don’t care
