9E4101AFILF Datasheet 9E4101AFILFT, 9E4101AFILF | P7-P9

IDT

TM

Programmable Timing Control Hub

TM

for Intel Systems 1408A—01/25/10

ICS9E4101

Programmable Timing Control Hub

TM

for Intel Systems

7

I

2

C Table: Output Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

SRC Stop Drive Mode

Drive Mode in

PCI_Stop

RW Driven Hi-Z

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

SRC PD Drive Mode

Drive Mode in PD

RW Driven Hi-Z 0

Bit 2

CPUCLK_ITP

Drive Mode in PD

RW Driven Hi-Z 0

Bit 1

CPUCLK1

Drive mode in PD

RW Driven Hi-Z 0

Bit 0

CPUCLK0

Drive mode in PD

RW Driven Hi-Z 0

I

2

C Table: Output Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

Test Mode Selection

Test Mode

Selection

RW Hi-Z REF/N 0

Bit 6

Test Clock Mode Entry Test Mode RW Disable Enable 0

Bit 5

0

Bit 4

REFOUT Stren

g

th Stren

g

th Pro

g

RW 1X 2X 1

Bit 3

PCI/SRC_STOP

Stop all PCI and

SRC clocks

RW

Enabled, all

stoppable PCI

and SRC

clocks are

stopped.

Disabled, all

stoppable PCI

and SRC clocks

are running

1

Bit 2

FS_

C

readback R - - LATCHED

Bit 1

FS_B readback R - - LATCHED

Bit 0

FS_A readback R - - LATCHED

I

2

C Table: Vendor & Revision ID Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

RID3 R - - 0

Bit 6

RID2 R - - 0

Bit 5

RID1 R - - 0

Bit 4

RID0 R - - 0

Bit 3

VID3 R - - 0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

I

2

C Table: Byte Count Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

BC7 RW - - 0

Bit 6

BC6 RW - - 0

Bit 5

BC5 RW - - 0

Bit 4

BC4 RW - - 0

Bit 3

BC3 RW - - 1

Bit 2

BC2 RW - - 0

Bit 1

BC1 RW - - 0

Bit 0

BC0 RW - - 0

-

B

y

te 5

B

y

te 6

19,20,22,23,

24,25,26,27,30,31,

32,33,35,36

RESERVED

17,18,19,20,22,23,

24,25,26,27,30,31,

32,33,35,36

54,55,56,3,4,5,8,9,

10

19,20,22,23,

24,25,26,27,30,31,

32,33,35,36

35,36

REVISION ID

RESERVED

-

40,41

43,44

52

-

RESERVED

-

VENDOR ID

-

B

y

te 7

-

B

y

te 8

-

Writing to this

register will

configure how

many bytes will be

read back, default

is 08

= 8 bytes.

-

IDT

TM

Programmable Timing Control Hub

TM

for Intel Systems 1408A—01/25/10

ICS9E4101

Programmable Timing Control Hub

TM

for Intel Systems

8

I

2

C Table: Watchdog Timer Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

WD4 RW - - 0

Bit 3

WD3 RW - - 0

Bit 2

WD2 RW - - 0

Bit 1

WD1 RW - - 0

Bit 0

WD0 RW - - 0

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 6

WDEN Watchdog Enable R Disable Enable 1

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

I

2

C Table: VCO Frequency Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

N Div8 N Divider Bit 8 RW - - X

Bit 6

M Div6 RW - - X

Bit 5

M Div5 RW - - X

Bit 4

M Div4 RW - - X

Bit 3

M Div3 RW - - X

Bit 2

M Div2 RW - - X

Bit 1

M Div1 RW - - X

Bit 0

M Div0 RW - - X

I

2

C Table: VCO Frequency Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

N Div7 RW - - X

Bit 6

N Div6 RW - - X

Bit 5

N Div5 RW - - X

Bit 4

N Div4 RW - - X

Bit 3

N Div3 RW - - X

Bit 2

N Div2 RW - - X

Bit 1

N Div1 RW - - X

Bit 0

N Div0 RW - - X

I

2

C Table: Spread Spectrum Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

SSP7 RW - - X

Bit 6

SSP6 RW - - X

Bit 5

SSP5 RW - - X

Bit 4

SSP4 RW - - X

Bit 3

SSP3 RW - - X

Bit 2

SSP2 RW - - X

Bit 1

SSP1 RW - - X

Bit 0

SSP0 RW - - X

0M/NEN

M/N Programming

Enable RW Disable

-

Enables

prograaming bytes

10-19

B

y

te 9

-

I

2

C Table: VCO Control Select Bit & WD Timer Control Re

g

ister

B

y

te 10

Bit 7

The decimal

representation of M

Div (6:0) is equal to

reference divider

value. Default at

power up = latch-in

or Byte 0 Rom

B

y

te 11

-

The decimal

representation of N

Div (8:0) is equal to

VCO divider value.

Default at power up

= latch-in or Byte 0

Rom table.

B

y

te 12

-

These Spread

Spectrum bits will

program the spread

pecentage. It is

recommended to

use ICS Spread %

table for spread

pro

g

rammin

g

.

B

y

te 13

-

RESERVED

Enable

RESERVED

IDT

TM

Programmable Timing Control Hub

TM

for Intel Systems 1408A—01/25/10

ICS9E4101

Programmable Timing Control Hub

TM

for Intel Systems

9

I

2

C Table: Spread Spectrum Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

0

Bit 6

0

Bit 5

SSP13 RW - - X

Bit 4

SSP12 RW - - X

Bit 3

SSP11 RW - - X

Bit 2

SSP10 RW - - X

Bit 1

SSP9 RW - - X

Bit 0

SSP8 RW - - X

I

2

C Table: Out

p

ut Divider Control Re

g

ister

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

SRC Div3 RW X

Bit 6

SRC Div2 RW X

Bit 5

SRC Div1 RW X

Bit 4

SRC Div0 RW X

Bit 3

CPU Div3 RW X

Bit 2

CPU Div2 RW X

Bit 1

CPU Div1 RW X

Bit 0

CPU Div0 RW X

I

2

C Table: Out

p

ut Divider Control Re

g

ister

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

PCI Div3 RW X

Bit 2

PCI Div2 RW X

Bit 1

PCI Div1 RW X

Bit 0

PCI Div0 RW X

I

2

C Table: Vendor & Revision ID Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

0

Bit 6

PCIINV PCI Phase Invert RW Default Inverse 0

Bit 5

SRCINV SRC Phase Invert RW Default Inverse 0

Bit 4

CPUINV CPU Phase Invert RW Default Inverse 0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

I

2

C Table: Group Skew Control Register

Pin # Nam

e

Control Function T

yp

e0 1 PWD

Bit 7

SRC_Skw3 RW 0

Bit 6

SRC_Skw2 RW 0

Bit 5

SRC_Skw1 RW 0

Bit 4

SRC_Skw0 RW 0

Bit 3

CPU_Skw3 RW 0

Bit 2

CPU_Skw2 RW 0

Bit 1

CPU_Skw1 RW 0

Bit 0

CPU_Skw0 RW 0

SRC Skew Control

CPU Skew Control

-

It is recommended

to use ICS Spread

% table for spread

programming.

B

y

te 14

-

B

y

te 15

- SRC divider ratio

can be configured

via these 4 bits

individually.

-

- CPU divider ratio

can be configured

via these 4 bits

individually.

-

B

y

te 16

- PCI divider ratio

can be configured

via these 4 bits

individually.

-

See Table: Divider Ratio

Combination Table

B

y

te 18

B

y

te 17

-

See Table: 7-Steps Skew

Programming Table

See Table: 7-Steps Skew

Programming Table

-

RESERVED

See Table: Divider Ratio

Combination Table

See Table: Divider Ratio

Combination Table

RESERVED

9E4101AFILF

9E4101AFILF

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