Document Number: 38-07273 Rev. *H Page 4 of 9
AC Electrical Specifications
(V
DD
= 3.3 V ± 10%, T
A
= 0 °C to 70 °C)
Parameter Description Conditions Min Typ Max Unit
IFR Input frequency range 44 48 52 MHz
t
r
Rise time
[4, 5]
–12ns
t
f
Fall time
[4, 5]
–12ns
SS% Spread spectrum percentage SSON# = 0, SSSEL = 0 – –1 – %
SSON# = 0, SSSEL = 1 – –3 – %
t
PU
Power-up to stable output
[6]
All output clocks – – 3 ms
t
DC
Clock duty cycle
[4, 6]
CL = 15 pF 45 50 55 %
t
CCJ
REFOUT cycle-to-cycle jitter
[4, 6]
CL = 15 pF – – 350 ps
CLKOUT cycle-to-cycle jitter
[4, 6]
–100250ps
Application Schematic Example
Figure 3. Application Schematic Example
[7, 8]
X IN
XOUT
C L2
C L1
0.1uF
33
33
V D D
REFOUT
CLKOUT
CY27020
1
7
5
4
SSSEL
S S O N #
8
6
VSS
3
2
VSS
VSS
48 MHz
VDD
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. All outputs loaded with
15 pF.
5. Measured between 0.1 x V
DD
and 0.9 x V
DD
volts.
6. Triggering is done at 1.5 V.
7. The circuit shows -1.0% spread. Refer to Frequency Table on page 1 for details.
8. Use the crystal manufacturer’s recommended values for CL1 and CL2 load capacitors.
