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AD660AR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD660
Rev. B | Page 9 of 20
TERMINOLOGY
Integral Nonlinearity
Integral nonlinearity is the maximum deviation of the actual,
adjusted DAC output from the ideal analog output (a straight
line drawn from 0 to FS − 1 LSB) for any bit combination. This
is also referred to as relative accuracy.
Differential Nonlinearity
Differential nonlinearity is the measure of the change in the
analog output, normalized to full scale, associated with a 1 LSB
change in the digital input code. Monotonic behavior requires
that the differential linearity error be greater than or equal to
−1 LSB over the temperature range of interest.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital inputs with the result that the
output is always a single-valued function of the input.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out.
Offset Error
Offset error is a combination of the offset errors of the voltage-
mode DAC and the output amplifier and is measured with all 0s
loaded in the DAC.
Bipolar Zero Error
When the AD660 is connected for bipolar output and 10…000
is loaded in the DAC, the deviation of the analog output from
the ideal midscale value of 0 V is called the bipolar zero error.
Drift
Drift is the change in a parameter (such as gain, offset, and bipolar
zero) over a specified temperature range. The drift temperature
coefficient, specified in ppm/°C, is calculated by measuring the
parameter at T
MIN
, 25°C, and T
MAX
, and dividing the change in
the parameter by the corresponding temperature change.
Total Harmonic Distortion + Noise
Total harmonic distortion + noise (THD + N) is defined as the
ratio of the square root of the sum of the squares of the values of
the harmonics and noise to the value of the fundamental input
frequency. It is usually expressed in percent (%).
THD + N is a measure of the magnitude and distribution of
linearity error, differential linearity error, quantization error,
and noise. The distribution of these errors may be different,
depending upon the amplitude of the output signal. Therefore,
to be the most useful, THD + N should be specified for both
large and small signal amplitudes.
Signal-To-Noise Ratio
The signal-to-noise ratio is the ratio of the amplitude of the output
when a full-scale signal is present to the output with no signal
present. The signal-to-noise ratio is measured in decibels (dB).
Digital-To-Analog Glitch Impulse
Digital-to-analog glitch impulse is the amount of charge
injected from the digital inputs to the analog output when the
inputs change state. This is measured at half scale when the DAC
switches around the MSB and as many as possible switches
change state, that is, from 011…111 to 100…000.
Digital Feedthrough
When the DAC is not selected (that is,
CS
is held high), high
frequency logic activity on the digital inputs is capacitively
coupled through the device to show up as noise on the V
OUT
pin.
This noise is digital feedthrough.
AD660
Rev. B | Page 10 of 20
THEORY OF OPERATION
The AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to the
applied digital word, ranging from 0 mA to 2 mA. A segmented
architecture is used, where the most significant four data bits
are thermometer decoded to drive 15 equal current sources.
The lesser bits are scaled using a R-2R ladder, then applied
together with the segmented sources to the summing node of
the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to 10 V
span, or it can be connected to the reference input to provide a
−10 V to +10 V span.
HBE
CONTROL
LOGIC
SER
CLR
LDAC
REF IN
10kΩ
10kΩ
10.05kΩ
REF OUT
DB0/
DB8/
SIN
DB1/DB9/
DATADIR
CS
DB7/
DB15
AD660
S
OUT
V
OUT
AGND
SPAN/
BIPOLAR
OFFSET
DGND
–V
EE
+V
CC
+V
LL
10V REF
16-BIT LATCH
16-BIT DAC
16-BIT LATCH
16
17
18
19
23
24
20
21
22
13
5
1 2 3 4
11121415
01813-007
LBE/
CLEAR SELECT
Figure 7. Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD660 can be connected
to produce a unipolar output range of 0 V to 10 V or a bipolar
output range of −10 V to +10 V. Gain and offset drift are mini-
mized in the AD660 because of the thermal tracking of the
scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 8 provides a unipolar 0 V to
10 V output range. In this mode, 50 Ω resistors are tied between
the SPAN/BIPOLAR OFFSET terminal (Pin 22) and V
OUT
(Pin 21),
and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible
to use the AD660 without any external components by tying Pin 24
directly to Pin 23 and Pin 22 directly to Pin 21. Eliminating
these resistors increases the gain error by 0.25% of FSR.
HBE
CONTROL
LOGIC
SER
CLR
LDAC
REF IN
REF OUT
AD660
S
OUT
V
OUT
AGND
OUTPUT
R2
50Ω
R1
50Ω
SPAN/
BIPOLAR
OFFSET
DGND
–V
EE
+V
CC
+V
LL
10V REF
16-BIT LATCH
16-BIT DAC
16
17
18
19
23
24
20
21
22
13
1 2 3 4
15
01813-008
10kΩ
10kΩ
10.05kΩ
DB1/DB9/
DATADIR
11
LBE/
CLEAR SELECT
DB0/
DB8/
SIN
CS
DB7/
DB15
51214
16-BIT LATCH
Figure 8. 0 V to 10 V Unipolar Voltage Output
If it is desired to adjust the gain and offset errors to zero, this
can be accomplished using the circuit shown in Figure 9. The
adjustment procedure is as follows:
1. Zero adjust.
Turn all bits off and adjust the zero trimmer, R4, until the
output reads 0.000000 V (1 LSB = 153 μV).
2. Gain adjust.
Turn all bits on and adjust the gain trimmer, R1, until the
output is 9.999847 V. (Full scale is adjusted to 1 LSB less
than the nominal full scale of 10.000000 V.)
HBE
CONTROL
LOGIC
SER
CLR
LDAC
REF IN
REF OUT
AD660
S
OUT
V
OUT
AGND
OUTPUT
R2
50Ω
R3
16k
R4
10k
R1
100Ω
SPAN/
BIPOLAR
OFFSET
DGND
–V
EE
+V
CC
–V
EE
+V
CC
+V
LL
10V REF
16-BIT LATCH
16-BIT DAC
16
17
18
19
23
24
20
21
22
13
1 2 3 4
15
01813-009
10kΩ
10kΩ
10.05kΩ
DB1/DB9/
DATADIR
11
LBE/
CLEAR SELECT
DB0/
DB8/
SIN
CS
DB7/
DB15
51214
16-BIT LATCH
Figure 9. 0 V to 10 V Unipolar Voltage Output with Gain and Offset
Adjustment
AD660
Rev. B | Page 11 of 20
BIPOLAR CONFIGURATION
The circuit shown in Figure 10 provides a bipolar output voltage
from −10.000000 V to +9.999694 V with positive full scale occur-
ring with all bits on. As in the unipolar mode, Resistor R1 and
Resistor R2 can be eliminated altogether to provide AD660 bipolar
operation without any external components. Eliminating these
resistors increases the gain error by 0.50% of FSR in bipolar mode.
HBE
CONTROL
LOGIC
SER
CLR
LDAC
REF IN
R1
50Ω
R2
50Ω
REF OUT
AD660
S
OUT
V
OUT
AGND
SPAN/
BIPOLAR
OFFSET
DGND
–V
EE
+V
CC
+V
LL
10V REF
16-BIT LATCH
16-BIT DAC
16
17
18
19
23
24
20
21
22
13
1 2 3 4
15
01813-010
OUTPUT
10kΩ
10kΩ
10.05kΩ
DB1/DB9/
DATADIR
11
LBE/
CLEAR SELECT
DB0/
DB8/
SIN
CS
DB7/
DB15
51214
16-BIT LATCH
Figure 10. ±10 V Bipolar Voltage Output
Gain offset and bipolar zero errors can be adjusted to zero using
the circuit shown in Figure 11 as follows:
1. Offset adjust.
Turn off all bits. Adjust the trimmer, R2, to give 10.000000 V
output.
2. Gain adjust.
Turn all bits on and adjust R1 to give a reading of 9.999694 V.
3. Bipolar zero adjust (optional).
In applications where an accurate zero output is required, set
the MSB on, all other bits off, and readjust R2 for 0 V output.
HBE
CONTROL
LOGIC
SER
CLR
LDAC
REF IN
R1
50Ω
REF OUT
AD660
S
OUT
V
OUT
AGND
SPAN/
BIPOLAR
OFFSET
DGND
–V
EE
+V
CC
+V
LL
10V REF
16-BIT LATCH
16-BIT DAC
16
17
18
19
23
24
20
21
22
13
1 2 3 4
15
01813-011
OUTPUT
R2
100Ω
10kΩ
10kΩ
10.05kΩ
DB1/DB9/
DATADIR
11
LBE/
CLEAR SELECT
DB0/
DB8/
SIN
CS
DB7/
DB15
51214
16-BIT LATCH
Figure 11. ±10 V Bipolar Voltage Output with Gain and Offset Adjustment
Note that using external resistors introduces a small temperature
drift component beyond that inherent in the AD660. The inter-
nal resistors are trimmed to ratio-match and temperature-track
other resistors on-chip, even though their absolute tolerances are
±20% and absolute temperature coefficients are approximately
−50 ppm/°C. In the case that external resistors are used, the
temperature coefficient mismatch between internal and external
resistors, multiplied by the sensitivity of the circuit to variations
in the external resistor value, is the resultant additional tempera-
ture drift.
INTERNAL/EXTERNAL REFERENCE USE
The AD660 has an internal low noise buried Zener diode
reference that is trimmed for absolute accuracy and temperature
coefficient. This reference is buffered and optimized for use in a
high speed DAC and gives long-term stability equal or superior to
the best discrete Zener diode references. The performance of
the AD660 is specified with the internal reference driving the
DAC and with the DAC alone (for use with a precision external
reference).
The internal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically 1 mA to REF IN and 1 mA to SPAN/BIPOLAR
OFFSET). A minimum of 2 mA is available for driving external
loads. The AD660 reference output should be buffered with an
external op amp if it is required to supply more than 4 mA total
current. The reference is tested and guaranteed to ±0.2%
maximum error.
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AD660AR

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Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC MONO 16-BIT
Lifecycle:
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