RMLV0414E Series
R10DS0216EJ0200 Rev.2.00 Page 12 of 12
2016.1.12
Low V
CC
Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*27
V
CC
for data retention V
DR
1.5 ─ ─ V
Vin ≥ 0V,
(1) CS# ≥ V
CC
-0.2V or
(2) LB# = UB# ≥ V
CC
-0.2V,
CS# ≤ 0.2V
Data retention current I
CCDR
─ 0.4
*26
2 A ~+25°C
V
CC
=3.0V, Vin ≥ 0V,
(1) CS# ≥ V
CC
-0.2V or
(2) LB# = UB# ≥ V
CC
-0.2V,
CS# ≤ 0.2V
─ ─ 3 A ~+40°C
─ ─ 5 A ~+70°C
─ ─ 7 A ~+85°C
Chip deselect time to data retention t
CDR
0 ─ ─ ns
See retention waveform.
Operation recovery time t
R
5 ─ ─ ms
Note 26. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
27. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and I/O buffer. If CS# controls
data retention mode, Vin levels (address, WE#, OE#, LB#,UB#, I/O) can be in the high-impedance state.
Low Vcc Data Retention Timing Waveforms (CS# controlled)
Low Vcc Data Retention Timing Waveforms (LB#,UB# controlled)
CS#
V
CC
CS# Controlled
t
CDR
t
R
2.7V 2.7V
2.2V 2.2V
DR
CS# ≥
- 0.2V
LB#,UB#
V
CC
LB#,UB# Controlled
t
CDR
t
R
2.7V 2.7V
2.2V 2.2V
DR
LB#
UB# ≥
- 0.2V
