NVT2003_04_06 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 February 2014 8 of 33
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled
to HIGH side V
pu(D)
through a pull-up resistor (typically 200 k). This allows VREFB to
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn
outputs to V
pu(D)
). However, if either output is totem-pole, data must be unidirectional or
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (V
ref(A)
) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V V
pu(D)
power supply, and V
ref(A)
is set between 1.0 V and (V
pu(D)
1 V), the output of each An
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to V
pu(D)
.
7.3 Bidirectional level shifting between two different power domains
nominally at the same potential
The less obvious application for the NVT2003 is for level shifting between two different
power domains that are nominally at the same potential, such as a 3.3 V system where
the line crosses power supply domains that under normal operation would be at 3.3 V, but
one could be at 3.0 V and the other at 3.6 V, or one could be experiencing a power failure
while the other domain is trying to operate. One of the NVT2003 three channel transistors
is used as a second reference transistor with its B side connected to a voltage supply that
is at least 1 V (and preferably 1.5 V) above the maximum possible for either V
pu(A)
or
V
pu(B)
. Then if either pull-up voltage is at 0 V, the channels are disabled, and otherwise the
channels are biased such that they turn OFF at the lower pull-up voltage, and if the two
pull-up voltages are equal, the channel is biased such that it just turns OFF at the
common pull-up voltage.
