LTC2859/LTC2861
10
285961fc
Driver
The driver provides full RS485 and RS422 compatibility.
When enabled, if DI is high, Y-Z is positive for the full
duplex device (LTC2861) and A-B is positive for the half-
duplex device (LTC2859).
When the driver is disabled, both outputs are high-
impedance. For the full duplex LTC2861, the leakage on
the driver output pins is guaranteed to be less than 10µA
over the entire common mode range of –7V to +12V. On
the half-duplex LTC2859, the impedance is dominated by
the receiver input resistance, R
IN
.
Driver Overvoltage and Overcurrent Protection
The driver outputs are protected from short circuits to
any voltage within the Absolute Maximum range of (V
CC
–15V) to +15V. The maximum current in this condition
is 250mA. If the pin voltage exceeds about ±10V, current
limit folds back to about half of the peak value to reduce
overall power dissipation and avoid damaging the part.
The LTC2859/LTC2861 also feature thermal shutdown
protection that disables the driver, terminator, and receiver
in case of excessive power dissipation.
SLO Mode: Slew Limiting for EMI Emissions Control
The LTC2859/LTC2861 feature a logic-selectable reduced-
slew mode (SLO mode) that softens
the driver output
edges to control the high frequency EMI emissions from
equipment and data cables. The reduced slew rate mode
is entered by taking the SLO pin low, where the data rate is
limited to about 250kbps. Slew limiting also mitigates the
adverse effects of imperfect transmission line termination
caused by stubs or mismatched cables.
Figures 8a and 8b show the LTC2861 driver outputs in
normal and SLO mode with their corresponding frequency
spectrums operating at 250kbps. SLO mode significantly
reduces the high frequency harmonics.
Figure 8a. Driver Output in Normal Mode
Driver Output at 125kHz into 100 Resistor Frequency Spectrum of the Same Signal
Figure 8b. Driver Output in SLO Mode
Driver Output at 125kHz into 100 Resistor Frequency Spectrum of the Same Signal
applicaTions inFormaTion
285961 F08a
Y, Z
Y–Z
2µs/DIV1V/DIV
Y–Z
1.25MHz/DIV10dB/DIV
285961 F08b
Y, Z
Y–Z
2µs/DIV1V/DIV
Y–Z
1.25MHz/DIV10dB/DIV
LTC2859/LTC2861
11
285961fc
Receiver and Failsafe
With the receiver enabled, when the absolute value of the
differential voltage between the A and B pins is greater than
200mV, the state of RO will reflect the polarity of (A-B).
The LTC2859/LTC2861 have a failsafe feature that guaran-
tees the receiver output to be in a logic HIGH state when
the inputs are either shorted, left open, or terminated
(externally or internally), but not driven for more than
abouts. The delay prevents signal zero crossings from
being interpreted as shorted inputs and causing RO to go
high inadvertently. This failsafe feature is guaranteed to
work for inputs spanning the entire common mode range
of –7V to +12V.
The receiver output is internally driven high (to V
CC
) or
low (to ground) with no external pull-up needed. When the
receiver is disabled the RO pin becomes Hi-Z with leakage
of less than ±1µA for voltages within the supply range.
Receiver Input Resistance
The receiver input resistance from A or B to ground is
greater than 96k permitting up to a total of 256 receivers
per system without exceeding the RS485 receiver load-
ing specification. High temperature H-Grade operation
reduces the minimum input
resistance to 48k permitting
128 receivers on the bus. The input resistance of the
receiver is unaffected by enabling/disabling the receiver
or by powering/unpowering the part. The equivalent input
resistance looking into A and B is shown in Figure 9.
Switchable Termination
Proper cable termination is very important for good signal
fidelity. If the cable is not terminated with its characteristic
impedance, reflections will result in distorted waveforms.
The LTC2859/LTC2861 are the first RS485 transceivers
to offer integrated switchable termination resistors on the
receiver input pins. This provides the tremendous advan-
tage of being able to easily change, through logic control,
the proper line termination for optimal performance when
configuring transceiver networks.
When the TE pin is high, the termination resistor is en-
abled and the differential resistance from A to B is 120Ω.
Figure 10 shows the I/V characteristics between pins A
and B with the termination resistor enabled and disabled.
The resistance is maintained over the entire RS485 com-
mon mode range of –7V to +12V as shown in Figure 11.
Figure 10. Curve Trace Between A and B
with Termination Enabled and Disabled
Figure 9. Equivalent Input Resistance into A and B
(on the LTC2859, Valid if Driver is Disabled)
applicaTions inFormaTion
60Ω
60Ω
A
TE
B
2859/61 F09
>96k
>96k
LTC2859/LTC2861
12
285961fc
The integrated termination resistor has a high frequency
response which does not limit performance at the maxi-
mum specified data rate. Figure 12 shows the magnitude
and phase of the termination impedance vs frequency. The
termination resistor cannot be enabled by TE if the device
is unpowered or in thermal shutdown mode.
Supply Current
The unloaded static supply currents in the LTC2859/
LTC2861 are very lowtypically under 700µA for all modes
of operation without the internal terminator enabled. In
applications with resistively terminated cables, the supply
current is dominated by the driver load. For example, when
using two 120terminators with a differential driver output
voltage of 2V, the DC current is 33mA, which is sourced
by the positive voltage supply. This is true whether the
terminators are external or internal such as in the LTC2859/
LTC2861. Power supply current increases with toggling
data due to capacitive loading and this term can increase
significantly at high data rates. Figure 13 shows supply
current vs data rate for two different capacitive loads (for
the circuit configuration of Figure 3).
High Speed Considerations
A ground plane layout is recommended for the LTC2859/
LTC2861. A 0.1µF bypass capacitor less than one quarter
inch
away from the V
CC
pin is also recommended. The PC
board traces connected to signals A/B and Z/Y (LTC2861)
should be symmetrical and as short as possible to maintain
good differential signal integrity. To minimize capacitive
effects, the differential signals should be separated by
more than the width of a trace and should not be routed
on top of each other if they are on different signal planes.
Care should be taken to route outputs away from any sen-
sitive inputs to reduce feedback effects that might cause
noise, jitter, or even oscillations. For example, in the full
duplex LTC2861, DI and A/B should not be routed near
the driver or receiver outputs.
The logic inputs of the LTC2859/LTC2861 have 50mV of
hysteresis to provide noise immunity. Fast edges on the
outputs can cause glitches in the ground and power supplies
which are exacerbated by capacitive loading. If a logic input
is held near its threshold (typically 1.5V), a noise glitch
Figure 11. Termination Resistance
vs Common Mode Voltage
Figure 12. Termination Magnitude
and Phase vs Frequency
Figure 13. Supply Current vs Data Rate
applicaTions inFormaTion
COMMON MODE VOLTAGE (V)
–10
RESISTANCE (Ω)
130
140
10
285961 F11
120
110
–5
0
5
15
150
10
–1
10
0
FREQUENCY (MHz)
MAGNITUDE (Ω)
PHASE (°)
10
1
80
95
110
125
140
155
170
185
–75
–60
–45
–30
–15
0
15
30
285455 F12
MAGNITUDE
PHASE
10
5
DATA RATE (kbps)
10
2
45
50
55
60
65
70
75
CURRENT (mA)
10
3
10
4
285961 F13
R
DIFF
= 54Ω
C
L
= 1000pF
C
L
= 100pF

LTC2859IDD#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RS-485 Interface IC 5V Half-Duplex RS485 Transceiver w/ Integrated Termination & Slew Rate Control
Lifecycle:
New from this manufacturer.
Delivery:
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