16
LTC1538-AUX/LTC1539
APPLICATIONS INFORMATION
WUU
U
+
+
V
IN
V
IN
V
OUT
+
C
OUT
1538 F04b
1µF
0.22µF
R
SENSE
C
IN
TGL1
N-CH
N-CH
N-CH
VN2222LL
LTC1538-AUX 
LTC1539*
L1
BAT85
BAT85
BAT85
TGS1*
SW1
BG1
PGND
EXTV
CC
*TGS1 ONLY AVAILABLE ON THE LTC1539
+
+
+
V
IN
V
IN
V
SEC
V
OUT
C
OUT
1538 F04a
1µF
R
SENSE
C
IN
TGL1
N-CH
OPTIONAL EXTV
CC
CONNECTION 
5V V
SEC
9V
N-CH
R5
N-CH
1N4148
LTC1538-AUX 
LTC1539*
L1
1:1
TGS1*
SW1
BG1
PGNDSGND
SFB1
EXTV
CC
R6
*TGS1 ONLY AVAILABLE ON THE LTC1539
Figure 4a. Secondary Output Loop and EXTV
CC
Connection Figure 4b. Capacitive Charge Pump for EXTV
CC
greater than 4.8V. This can be done with either the
inductive boost winding as shown in Figure 4a or the
capacitive charge pump shown in Figure 4b. The charge
pump has the advantage of simple magnetics.
4. EXTV
CC
connected to an external supply. If an external
supply is available in the 5V to 10V range (EXTV
CC
V
IN
)
it may be used to power EXTV
CC
providing it is compat-
ible with the MOSFET gate drive requirements. When
driving standard threshold MOSFETs, the external sup-
ply must be always present during operation to prevent
MOSFET failure due to insufficient gate drive. Note: care
must be taken when using the connections in items 3 or
4. These connections will effect the INTV
CC
voltage
when either or both controllers are on.
Topside MOSFET Driver Supply (C
B
,D
B
)
External bootstrap capacitors C
B
connected to the BOOST
1 and BOOST 2 pins supply the gate drive voltages for the
topside MOSFETs. Capacitor C
B
in the Functional Diagram
is charged through diode D
B
from INTV
CC
when the
SW1(SW2) pin is low. When one of the topside MOSFETs
is to be turned on, the driver places the C
B
voltage across
the gate source of the desired MOSFET. This enhances the
MOSFET and turns on the topside switch. The switch node
voltage SW1(SW2) rises to V
IN
and the BOOST 1(BOOST
2) pin follows. With the topside MOSFET on, the boost
voltage is above the input supply: V
BOOST
= V
IN
+ V
INTVCC
.
The value of the boost capacitor C
B
needs to be 100 times
that of the total input capacitance of the topside MOSFET(s).
The reverse breakdown on D
B
must be greater than
V
IN(MAX)
.
Output Voltage Programming
The LTC1538-AUX/LTC1539 have pin selectable output
voltage programming. The output voltage is selected by
the V
PROG1
(V
PROG2
) pin as follows:
V
PROG1,2
= 0V V
OUT1,2
= 3.3V
V
PROG1,2
= INTV
CC
V
OUT1,2
= 5V
V
PROG2
= Open (DC) V
OUT2
= Adjustable
The top of an internal resistive divider is connected to
SENSE
1 pin in Controller 1. For fixed output voltage
applications the SENSE
1 pin is connected to the output
voltage as shown in Figure 5a. When using an external
resistive divider for Controller 2, the V
PROG2
pin is left open
LTC1538-AUX
LTC1539
V
PROG2
*
V
OSENSE2
SGND
OPEN (DC)
1.19V V
OUT
9V
1538 F05b
100pF
R2
R1
R2
R1
V
OUT
= 1.19V 1 +
()
*LTC1539 ONLY
Figure 5b. LTC1538-AUX/LTC1539 Adjustable Applications
Figure 5a. LTC1538-AUX/LTC1539 Fixed Output Applications
LTC1538-AUX
LTC1539
V
PROG1
SENSE
1
SGND
GND: V
OUT
= 3.3V
INTV
CC
: V
OUT
= 5V
+
V
OUT
1538 F05a
C
OUT
17
LTC1538-AUX/LTC1539
APPLICATIONS INFORMATION
WUU
U
(DC) and the V
OSENSE2
pin is connected to the feedback
resistors as shown in Figure 5b. Controller 2 will force the
externally attenuated output voltage to 1.19V.
Power-On Reset Function (POR)
The power-on reset function monitors the output voltage
of the first controller and turns on an open drain device
when it is below its properly regulated voltage. An external
pull-up resistor is required on the POR1 pin.
When power is first applied or when coming out of
shutdown, the POR1 output is held at ground. When the
output voltage rises above a level which is 5% below the final
regulated output value, an internal counter starts. After this
counter counts 2
16
(65536) clock cycles, the POR1 pull-
down device turns off. The POR1 output is active when both
controllers are shut down as long as V
IN
is powered.
The POR1 output will go low whenever the output voltage
of the first controller drops below 7.5% of its regulated
value for longer than approximately 30µs, signaling an
out-of-regulation condition. In shutdown, when RUN/SS1
and RUN/SS2 are both below 1.3V, the POR1 output is
pulled low even if the regulator’s output is held up by an
external source.
RUN/Soft Start Function
The RUN/SS1 and RUN/SS2 pins each serve two func-
tions. Each pin provides the soft start function and a
means to shut down each controller. Soft start reduces
surge currents from V
IN
by providing a gradual ramp-up of
the internal current limit.
Power supply sequencing
can
also be accomplished using this pin.
An internal 3µA current source charges up an external
capacitor C
SS.
When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.3V the particular controller is permitted to start
operating. As the voltage on the pin continues to ramp
from 1.3V to 2.4V, the internal current limit is also ramped
at a proportional linear rate. The current limit begins at
approximately 50mV/R
SENSE
(at V
RUN/SS
= 1.3V) and ends
at 150mV/R
SENSE
(V
RUN/SS
2.7V). The output current
thus ramps up slowly, reducing the starting surge current
required from the input power supply. If RUN/SS has been
pulled all the way to ground there is a delay before starting
of approximately 500ms/µF, followed by a similar time to
reach full current on that controller.
By pulling both RUN/SS controller pins below 1.3V, the
LTC1538-AUX/LTC1539 are put into shutdown
(I
Q
< 200µA). These pins can be driven directly from logic
as shown in Figure 6. Diode D1 in Figure 6 reduces the start
delay but allows C
SS
to ramp up slowly providing the soft
start function; this diode and C
SS
can be deleted if soft start
is not needed. Each RUN/SS pin has an internal 6V Zener
clamp (See Functional Diagram).
Foldback Current Limiting
As described in Power MOSFET and D1 Selection, the
worst-case dissipation for either MOSFET occurs with a
short-circuited output, when the synchronous MOSFET
conducts the current limit value almost continuously. In
most applications this will not cause excessive heating,
even for extended fault intervals. However, when heat
sinking is at a premium or higher R
DS(ON)
MOSFETs are
being used, foldback current limiting should be added to
reduce the current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding diode
D
FB
between the output and the I
TH
pin as shown in the
Functional Diagram. In a hard short (V
OUT
= 0V) the
current will be reduced to approximately 25% of the
maximum output current. This technique may be used for
all applications with regulated output voltages of 1.8V or
greater.
D1
C
SS
3.3V
OR 5V
RUN/SS1
(RUN/SS2)
C
SS
1538 F06
RUN/SS1
(RUN/SS2)
Figure 6. RUN/SS Pin Interfacing
18
LTC1538-AUX/LTC1539
APPLICATIONS INFORMATION
WUU
U
Figure 7. Operating Frequency vs V
PLLLPF
V
PLLLPF
(V)
0
NORMALIZED FREQUENCY
1.3
f
O
0.7
1538 F07
1.5 2.01.00.5
2.5
*PLLIN
SGND
50k
1538 F08
*PLL LPF C
OSC
PHASE 
DETECTOR*
OSC
R
LP
C
LP
C
OSC
EXTERNAL
FREQUENCY
2.4V
DIGITAL
PHASE/
FREQUENCY
DETECTOR
*LTC1539 ONLY
Figure 8. Phase-Locked Loop Block Diagram
Phase-Locked Loop and Frequency Synchronization
The LTC1539 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage-controlled oscillator is ±30% around the center
frequency f
O
.
The value of C
OSC
is calculated from the desired operating
frequency (f
O
). Assuming the phase-locked loop is
locked
(V
PLLLPF
= 1.19V):
CpF
Frequency kHz
OSC
()
.
()
=
()
2110
11
4
Stating the frequency as a function of V
PLLLPF
and C
OSC
:
Frequency kHz
CpF
AA
V
V
OSC
PLLLPF
()
.
.
=
()
()
+
[]
µ+ µ
+
8410
11
1
17 18
24
2000
8
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, f
H
, is equal to the capture range, f
C:
f
H
= f
C
= ±0.3 f
O
.
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLL LPF pin. A simplified block
diagram is shown in Figure 8.
If the external frequency f
PLLIN
is greater than the oscilla-
tor frequency f
OSC
, current is sourced continuously, pull-
ing up the PLL LPF pin. When the external frequency is less
than f
0SC
, current is sunk continuously, pulling down the
PLL LPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. Thus the voltage on the PLL LPF pin is adjusted
until the phase and frequency of the external and internal
oscillators are identical. At this stable operating point the
phase comparator output is open and the filter capacitor
C
LP
holds the voltage. The LTC1539 PLLIN pin must be
driven from a low impedance such as a logic gate located
close to the pin. Any external attenuator used needs to be
referenced to SGND.
The loop filter components C
LP
, R
LP
smooth out the
current pulses from the phase detector and provide a

LTC1539CGW#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Const Freq Syn Sw Reg Cntrl
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union