10
Figure 3. Recommended Gigabit/sec Ethernet AFBR-53D3 Fiber-Optic Transceiver and HDMP-1536A/1546A SERDES Integrated Circuit Transceiver Interface and
Power Supply Filter Circuits.
9
8
7
6
5
4
3
1
PECL
INPUT
OUTPUT
DRIVER
CLOCK
SYNTHESIS
CIRCUIT
PARALLEL
TO SERIAL
CIRCUIT
LASER
DRIVER
CIRCUIT
INPUT
BUFFER
CLOCK
RECOVERY
CIRCUIT
SERIAL TO
PARALLEL
CIRCUIT
PRE-
AMPLIFIER
POST-
AMPLIFIER
SIGNAL
DETECT
CIRCUIT
R10
270
TO SIGNAL DETECT (SD)
INPUT AT UPPER-LEVEL-IC
R11
270
50
R9
270
R14
100
C12 0.01 µF
C11 0.01 µF
2
C4
10
µF
C3
0.1
µF
5 V dc
C2
0.1 µF
C1
0.1
µF
C8*
10 µF*
L2
1 µH
L1
1 µH
C10 0.01 µF
C9 0.01 µF
C5
0.1 µF
R1
191
R4
191
R3
68
R2
68
5 V dc
R13
150
R12
150
50
50
50
+
+
+
3.3 V dc
GND
TD+
TD-
RD-
RD+
TD+
TD-
RD-
RD+
SD
V
CCR
V
CCT
V
EET
V
EER
AFBR-53D3
FIBER-OPTIC
TRANSCEIVER
HDMP-1536A/-1546A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
TRANSCEIVER)
NOTES:
*C8 IS AN OPTIONAL BYPASS CAPACITOR FOR ADDITIONAL LOW-FREQUENCY NOISE FILTERING.
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50 MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50 TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
V
CC2
V
EE2
SEE HDMP-1536A/-1546A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
Figure 4. Recommended Board Layout Hole Pattern.
(8X)
2.54
0.100
20.32
0.800
20.32
0.800
1.9 ± 0.1
0.075 ± 0.004
(2X)
ø
Ø0.000
M
A
0.8 ± 0.1
0.032 ± 0.004
(9X)
ø
Ø0.000
M
A
–A–
TOP VIEW
11
Figure 5. Package Outline Drawing for AFBR-53D3Z.
39.6
(1.56)
MAX.
AREA
RESERVED
FOR
PROCESS
PLUG
12.7
(0.50)
25.4
(1.00)
MAX.
12.7
(0.50)
20.32
(0.800)
20.32
(0.800)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ±0.025 mm UNLESS OTHERWISE SPECIFIED.
9.8
(0.386)
MAX.
+0.1
-0.05
0.25
+0.004
-0.002
(
0.010
3.3 ± 0.38
(0.130 ± 0.015)
8X
)
20.32
(0.800)
2.5
(0.10)
SLOT DEPTH
XXXX-XXXX
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
TX RX
SLOT WIDTH
4.7
(0.185)
23.8
(0.937)
+0.25
-0.05
0.46
+0.010
-0.002
(
0.018
)
9X Ø
1.3
(0.051)
2X
Ø
15.8 ± 0.15
(0.622 ± 0.006)
+0.25
-0.05
1.27
+0.010
-0.002
(
0.050
)
2X
Ø
2.0 ± 0.1
(0.079 ± 0.004)
KEY:
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = AFBR-53xx
ZZZZ = 850 nm
0.51
(0.020)
2.54
(0.100)
AVAGO
12
Figure 6. Package Outline for AFBR-53D3EZ.
39.6
(1.56)
MAX.
AREA
RESERVED
FOR
PROCESS
PLUG
12.7
(0.50)
25.4
(1.00)
MAX.
12.7
(0.50)
20.32
(0.800)
20.32
(0.800)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ±0.025 mm UNLESS OTHERWISE SPECIFIED.
9.8
(0.386)
MAX.
+0.1
-0.05
0.25
+0.004
-0.002
(
0.010
3.3 ± 0.38
(0.130 ± 0.015)
)
20.32
(0.80)
SLOT WIDTH
4.7
(0.185)
23.8
(0.937)
+0.25
-0.05
0.46
+0.010
-0.002
(
0.018
)
9X
Ø
1.3
(0.051)
2X
Ø
15.8 ± 0.15
(0.622 ± 0.006)
+0.25
-0.05
1.27
+0.010
-0.002
(
0.050
)
2X
Ø
2.0 ± 0.1
(0.079 ± 0.004)
29.6
(1.16)
KEY:
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = AFBR-53xx
ZZZZ = 850 nm
8X
2.54
(0.100)
10.2
(0.40)
1.3
(0.05)
MAX.
2.09
(0.08)
UNCOMPRESSED
UNCOMPRESSED
XXXX-XXXX
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
TX
RX
AVAGO

AFBR-53D3FZ

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Transmitters, Receivers, Transceivers MM 1x9 5V FC TXCBR Flushed Shield
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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