Regulation Loop Stability VIPer53EDIP - E / VIPer53ESP - E
16/31 DocRev1
10 Regulation Loop Stability
The complete converter open loop transfer function can be built from both power cell and
the feedback network transfer functions. A theoretical example can be seen in Figure 11 on
page 22 for a discontinuous mode flyback loaded by a simple resistor.
A typical schematic corresponding to this situation can be seen on Figure 3 on page 8. The
transfer function of the power cell is represented as G(s) in .Figure 11 on page 22 It exhibits
a pole which depends on the output load and on the output capacitor value. As the load of a
converter may change, two curves are shown for two different values of output resistance
value, R
L1
and R
L2
. A zero at higher frequency values then appears, due to the output
capacitor ESR. Note: The overall transfer function does not depend on the input voltage
because of the current mode control. A typical regulation loop is shown on Figure 3 on
page 8 and has a fixed behavior represented by F(s) on Figure 11 on page 22. A double
zero due to the R
1
-C
1
network on the COMP pin and to the integrator built around the TL431
and R
2
-C
2
is set at the same value as the maximum load R
L2
pole.
The total transfer function is shown as F(s). G(s) at the bottom of Figure 11 on page 22. For
maximum load (plain line), the load pole begins exactly where the zeros of the COMP pin
and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero
of the output capacitor ESR. The point where the complete transfer function has a unity gain
is known as the regulation bandwidth and has a double interest:
The higher it is, the faster the reaction will be to an eventual load change, and the
smaller the output voltage change will be.
The phase shift in the complete system at this point has to be less than 135° to
ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a
second-order gives 180°.
In Figure 3 on page 8, the unity gain is reached in a first order slope, so the stability is
ensured.
The dynamic load regulation is improved by increasing the regulation bandwidth, but some
limitations have to be respected:
1. As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself
is not well specified, and other parasitic effects may take place), the bandwidth should
always be lower than the minimum of FC and ESR zero
2. As the highest bandwidth is obtained with the highest output power (plain line with RL2
load in Figure 3, the above criteria will be checked for this condition and allows the
value of R4 if R1 is set to a fixed value (e.g., (2.2k).
As the highest bandwidth is obtained with the highest output power (Plain line with R
L2
load
in Figure 3), the above criteria will be checked for this condition and allows to define the
value of R
4
, if R1 is set fixed (2.2k, for instance). The following formula can be derived:
Go is the current transfer ratio of the optocoupler.
R
4
P
MAX
P
OUT2
---------------------
G
O
R
1
F
BW2
R
L2
C
OUT
⋅⋅
--------------------------------------------------------=
P
OUT2
V
OUT
2
R
L2
-----------------=
with:
P
MAX
1
2
--- L
P
I
LIM
2
F
SW
⋅⋅ =
and:
VIPer53EDIP - E / VIPer53ESP - E Regulation Loop Stability
DocRev1 17/31
The lowest load gives another condition for stability: The frequency F
BW1
must not
encounter the third order slope generated by the load pole, the R1-C1 network on the
COMP pin and the R2-C2 network at the level of the TL431 on secondary side. This
condition can be met by adjusting both C
1
and C2 values:
The above formula gives a minimum value for C1. It can be then increased to provide a
natural soft start function as this capacitor is charged by the current I
COMP
at start-up.
C
1
R
L1
C
OUT
6.3
G
O
R
4
--------- R
1
2
⋅⋅
---------------------------------- -
P
OUT1
P
MAX
--------------------->
C
2
R
L1
C
OUT
6.3
G
O
R
4
--------- R
1
R
2
⋅⋅
---------------------------------------------- -
P
OUT1
P
MAX
--------------------->
P
OUT1
V
OUT
2
R
L1
-------------------=
with:
Special Recommendations VIPer53EDIP - E / VIPer53ESP - E
18/31 DocRev1
11 Special Recommendations
10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to
ensure correct stability of the internal current source Figure 12 on page 22.
In order to improve the ruggedness of the device versus eventual drain overvoltages, a
resistance of 1k should be inserted in series with the TOVL pin, as shown on Figure 12 on
page 22
Note: This resistance does not impact the overload delay, as its value is negligible prior to the
internal pull-up resistance (about 125k
).

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